DDR PHY Training

[@Nuthouse01]

This is a pretty good video, but I was really looking for an introduction about what training is and why it needs to be done. This video feels like part 2 of a lecture where I was looking for part 1. The title is misleading.

[@pavankumarreddy7888]

Keep up the work you guys are doing.

[@briankamras2913]

I feel like there’s about 99% than what’s discussed here, but this was still a bit helpful.

[@anudeep1193]

Please provide references to learn more about "DDR PHY Training".

[@vishwasnarayan]

jeedaks specification what does it mean??

[@SperlingMediaGroup]

That's JEDEC, the Solid State Technology Association. You can find them at jedec.org

[@kohtaosunrise7354]

nice work, but sorry this video doesn't explain what the training is and how it really works and why (at low level)... like adjusting delays so each clock is centered to each data bit, impedance/reflection adjustment, etc.. maybe this kind of video should have in mind that public are beginners learning about it... the SI eye was given out of nowhere as a reference without explaining it is the superposition of different scenarios ...

[@tryssss]

hi guys, i'm now working on controller for DDR3 someone can send me Write leveling code and other read training vhdl or verilog.... thanks

[@ghtry5]

how much can you pay for it?

[@tryssss]

@@ghtry5 i already develop it thanks :)