DDR4 Part1

[@AndrewKiethBoggs]

This is amazing. Best format for this information

[@andrewyork3869]

Thank you for taking the time to make these videos, I always enjoy learning about hardware at a deeper level than I have in school.

[@GOPALJHAlife]

I am your fan Terry Fox Your videos have helped me to clear my basics 😊 I went through some online materials but your videos are best. Thanks a lot for sharing your knowledge.

[@maryamshahbazi6107]

Great video! 14 minutes, to the point. Thank you.

[@Saschaborg]

Thanks so much for this huge amount of valuable information!

[@epiendless1128]

DDR4 data voltage (AC) was shown on one slide as +-75mV and +-100mV on the next slide? Was one of them supposed to be DC?

[@tfoxwa]

I think you are looking at the difference between Addr, Cmd, Cntrl levels which work as Center Tap Terminated and DDR4 Data signals which are Partially Open Drain. One value for CTT signals and the other value for POD signals

[@phillipavila9225]

Pure fire 🔥

[@yongyan8111]

great tutorial, best regards to you

[@timpeng1269]

I thought DDR4 data group uses "pseudo" open drain.

[@tfoxwa]

Yes ..My error..TFox

[@timpeng1269]

Terry Fox no worries, it’s been a great video. Drop us more perspectives or tips when simulating ddr4 in hyperlynx.

[@asangajr]

Hi, Could I use balanced tree topology for clock/address/cmd instead of daisy-chained? The application is one host and two DDR4, expected running at 2400Mbps.

[@terryfox6236]

If you have a very small design...ie very few SDRAMs, you could theoretically make it work. I would NEVER do anything without simulating it first..TFox

[@asangajr]

Yes, it is a small form factor design. Thanks for your comment. BTW, these video series of DDRs and SI/PI are very good and helpful.