Design Guide for Bootstrap Gate Driver Circuit with LTspice Simulation

[@giangem37]

tks for video, that's very useful, but if we use this for buck circuit (not synchronus buck), at Ton when 2 mosfet M1 and M2 on (closed) at the Source point had buck voltage, so the M1 will short at this time, so this circuit will help for highside mosfet with resitor load? or am i wrong?

[@majidhyderi-jimmy5588]

Can you send me the link of simulation file?

[@prabhatkiran3226]

Thanks for the informative video. Can there be any disadvantages in selecting a too high value for Cbs? For example, if I use Cbs>1000*Cgs what will happen?

[@Charged_EE]

Disadvantages: 1000*Cgs capacitance will be costlier, It will also consume more board space if belong to same type (e.g. Ceramic) and lastly it will take longer to reach full voltage and hence transient performance will be slower.

[@prabhatkiran3226]

@@Charged_EE Thanks for the reply. If you don't mind, I have another question to ask. In many examples, I have seen another low-value capacitor used in parallel to Cbs. Is this necessary? Or will the circuit work just fine if I use just one appropriate capacitor?

[@Charged_EE]

@@prabhatkiran3226 depends upon your layout...if your boot-cap is located far from gate driver pins then you may want to put some low value bypass cap on the pin-out of the gate driver.. this is done to compensate drop in trace inductance and smoothen the waveform..

[@prabhatkiran3226]

@@Charged_EE Thanks man. You cleared my doubts.

[@memmedshamurov1639]

What about gate-source resistor around 10k?