Design Rule Check | DRC of Layout | Cadence Virtuoso | with Calibre | Calculator | Simulation

This cadence tutorial shows how to check DRC (Design Rule Checks) of Layout in Cadence Virtuoso using MetorGraphic's Calibre tool. Schematic Design and Simulation, use of Calculator in Virtuoso, Delay Calculation using Calculator in virtuoso, Symbol creation from schematics, Simulation of symbols in virtuoso, are some of the main highlights of this tutorial. How to Integrate the Calibre tool inside Cadence virtuoso has been explained in a separate video. Link is given bellow.
In this session -5 of the series, A schematic of a CMOS Inverter has been drawn and then we have simulated this using Spectre. We analyze the output waveform and also checked some basic function of Calculator. And using the Calculator we also checked the delay of the circuit. Then we have created the symbol from the schematic view and simulated the symbol also. After that, Layout has been drawn and performed Design Rule Check (DRC) using Mentorgraphics tool Calibre. In the next session, we will perform the LVS check and Parasitic Extraction (PEX) and then we will go for post-layout simulation and compare the results
Links of all the videos in this series are as follows
1. Layout of nmos:
• Layout design of nMOS ...
2. Layout of pMOS
• Layout Design of pMOS ...
3. Layout of BJT
• Layout design of BJT (...
4.Pcell Implementation
• Pcell (parametrized ce...
5. DRC check, Simulation and other explanations
• Design Rule Check | DR...
6. LVS, PEX and Post Layout Simulations
• LVS (Layout vs Schemat...
Integration of Calibre tool in Cadence Virtuoso
• Calibre EDA tool | Ins...
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