This video is about the layout design of a cmos NAND gate using Cadence Virtuoso tool. In this LVS of nand design is shown.
Пікірлер: 55
@picnicbros Жыл бұрын
Sir, I'm new to this and you helped me so much. Thank you!
@dr.hariprasadnaikbhattu Жыл бұрын
Thanks a lot for the response
@senthilsundaramp1953Ай бұрын
in 3:57 how did you pair both pmos ? it doesnt mean that drain of pmos1 and source of pmos2 is connected ?
@dr.hariprasadnaikbhattu25 күн бұрын
Hi, I have consider both as Drain and connected then as one you can see that in schematic.
@meghanaparusu94612 жыл бұрын
Sir please help me sir, Where can I find pass transistor sir I mean that transistor name sir like bsimp4 like that sir. I have Shannon adder by using pass transistor sir but I don't where it is sir
@dr.hariprasadnaikbhattu2 жыл бұрын
Hi, BSIM4 are the model or technology files used to simulate MOS circuits. They are not free. Instead use the ptm models ptm.asu.edu/
@meghanaparusu94612 жыл бұрын
@@dr.hariprasadnaikbhattu Thank you so much sir
@hoannguyen281911 ай бұрын
Is there a crack version of cadence virtuoso software to create this layout? I am a student who wants to practice it. There doesn't seem to be a free version to practice with
@dr.hariprasadnaikbhattu11 ай бұрын
Hi, check KZbin. Some are providing the links
@hoannguyen281911 ай бұрын
@@dr.hariprasadnaikbhattu yes, can you give me some of those links? I really want to learn layout while I'm still studying
@annguyenvan65606 ай бұрын
why can't I combine two series nmos like you? It still has three pins after
@dr.hariprasadnaikbhattu6 ай бұрын
Hi, in display options enable abutment
@annguyenvan65606 ай бұрын
@@dr.hariprasadnaikbhattu I can't find this option
@luisilichvladimirguerrerol23217 ай бұрын
I ❤. Quick question, how did you rotate the path when you were wiring the second gate?
@dr.hariprasadnaikbhattu7 ай бұрын
Kindly mention the time line of the video. So that I can answer
@nhutao90507 ай бұрын
How to know when pmos or nmos is detached or integrated sir ?
@dr.hariprasadnaikbhattu7 ай бұрын
Whether it is schematic or layout. In schematic they are detached. But in layout PMOS or NMOS are integrated. So need to detach
@nhutao9050Ай бұрын
@@dr.hariprasadnaikbhattu Thank you sir.
@meghanaparusu94612 жыл бұрын
Sir can you help me sir 🙏🙏 Layout is missed sir When i was editing the variables in OR GATE How can I reget it sir 🙏
@dr.hariprasadnaikbhattu2 жыл бұрын
1) First open schematic design 2) Launch (from schematic) -->Layout XL--> Open Existing
@dr.hariprasadnaikbhattu2 жыл бұрын
Hope this will help you.
@meghanaparusu94612 жыл бұрын
In the cell view when i opened or2 gate it is not visible sir. I mean when i am editing input variable name at that time the image or or gate had gone sir When i reopened it Even though it showing empty image sir
@kaveeshaweliwaththa2499 Жыл бұрын
I got the following error after DRC run. Any solution for this ? " Minimum dimension of an NW region not connected to the most positive power supply is 2.10um. Need to be changed depending on your power supply name In this case the most positive voltage "
@dr.hariprasadnaikbhattu Жыл бұрын
Try to increase the nwell region
@maansterminator Жыл бұрын
since it's layout it takes some time. yahhh bro I totally agree with you.
@dr.hariprasadnaikbhattu Жыл бұрын
You are Welcome
@sukasinikesavan9505 Жыл бұрын
Sir in gpdk90 where can we find assura option
@dr.hariprasadnaikbhattu Жыл бұрын
Assura is available in Layout XL
@anikarichie Жыл бұрын
Thank you so much sir!!
@dr.hariprasadnaikbhattu Жыл бұрын
Thanks for the Support
@kabandajamir9844 Жыл бұрын
So nice thanks sir
@dr.hariprasadnaikbhattu Жыл бұрын
Thanks 👍
@mbabu95762 ай бұрын
Thank you sir
@dr.hariprasadnaikbhattu2 ай бұрын
You are welcome
@dr.hariprasadnaikbhattu2 ай бұрын
Welcome
@mbabu95762 ай бұрын
@@dr.hariprasadnaikbhattu Hi sir how to estimate the area ? do we estimate area in schematic or in layout. please explain. thank you
@rahulbhattu76619 ай бұрын
Thanks
@dr.hariprasadnaikbhattu9 ай бұрын
Welcome
@BrindhaThanjavur2 жыл бұрын
Sir am doing for comparator circuit thats too big. I have some doubts. Can you share your mail id?
@dr.hariprasadnaikbhattu2 жыл бұрын
How can I help you?
@BrindhaThanjavur2 жыл бұрын
@@dr.hariprasadnaikbhattu My doubts are in layout sir. I am struggling how to do perfect layout. For me overlapping happens.
@BrindhaThanjavur2 жыл бұрын
@@dr.hariprasadnaikbhattu i followed your 90nm inverter layout. While am trying for comparator in in 180nm i couldnt place vdd and vss as rails.
@dr.hariprasadnaikbhattu2 жыл бұрын
@@BrindhaThanjavur madam you need to place vdd and vss in schematic also
@BrindhaThanjavur2 жыл бұрын
@@dr.hariprasadnaikbhattu Yes sir i gave. I follwed your video only.While fixing rails it says other pins will go and it cannot be undone.