Cadence Virtuoso:: Layout of NAND Gate || Part-2.

This video is about the layout design of a cmos NAND gate using Cadence Virtuoso tool. In this LVS of nand design is shown.

[@picnicbros]

Sir, I'm new to this and you helped me so much. Thank you!

[@dr.hariprasadnaikbhattu]

Thanks a lot for the response

[@senthilsundaramp1953]

in 3:57 how did you pair both pmos ? it doesnt mean that drain of pmos1 and source of pmos2 is connected ?

[@dr.hariprasadnaikbhattu]

Hi, I have consider both as Drain and connected then as one you can see that in schematic.

[@meghanaparusu9461]

Sir please help me sir, Where can I find pass transistor sir I mean that transistor name sir like bsimp4 like that sir. I have Shannon adder by using pass transistor sir but I don't where it is sir

[@dr.hariprasadnaikbhattu]

Hi, BSIM4 are the model or technology files used to simulate MOS circuits. They are not free. Instead use the ptm models ptm.asu.edu/

[@meghanaparusu9461]

@@dr.hariprasadnaikbhattu Thank you so much sir

[@hoannguyen2819]

Is there a crack version of cadence virtuoso software to create this layout? I am a student who wants to practice it. There doesn't seem to be a free version to practice with

[@dr.hariprasadnaikbhattu]

Hi, check KZbin. Some are providing the links

[@hoannguyen2819]

@@dr.hariprasadnaikbhattu yes, can you give me some of those links? I really want to learn layout while I'm still studying

[@annguyenvan6560]

why can't I combine two series nmos like you? It still has three pins after

[@dr.hariprasadnaikbhattu]

Hi, in display options enable abutment

[@annguyenvan6560]

@@dr.hariprasadnaikbhattu I can't find this option

[@luisilichvladimirguerrerol2321]

I ❤. Quick question, how did you rotate the path when you were wiring the second gate?

[@dr.hariprasadnaikbhattu]

Kindly mention the time line of the video. So that I can answer

[@nhutao9050]

How to know when pmos or nmos is detached or integrated sir ?

[@dr.hariprasadnaikbhattu]

Whether it is schematic or layout. In schematic they are detached. But in layout PMOS or NMOS are integrated. So need to detach

[@nhutao9050]

@@dr.hariprasadnaikbhattu Thank you sir.

[@meghanaparusu9461]

Sir can you help me sir 🙏🙏 Layout is missed sir When i was editing the variables in OR GATE How can I reget it sir 🙏

[@dr.hariprasadnaikbhattu]

1) First open schematic design 2) Launch (from schematic) -->Layout XL--> Open Existing

[@dr.hariprasadnaikbhattu]

Hope this will help you.

[@meghanaparusu9461]

In the cell view when i opened or2 gate it is not visible sir. I mean when i am editing input variable name at that time the image or or gate had gone sir When i reopened it Even though it showing empty image sir

[@kaveeshaweliwaththa2499]

I got the following error after DRC run. Any solution for this ? " Minimum dimension of an NW region not connected to the most positive power supply is 2.10um. Need to be changed depending on your power supply name In this case the most positive voltage "

[@dr.hariprasadnaikbhattu]

Try to increase the nwell region

[@maansterminator]

since it's layout it takes some time. yahhh bro I totally agree with you.

[@dr.hariprasadnaikbhattu]

You are Welcome

[@sukasinikesavan9505]

Sir in gpdk90 where can we find assura option

[@dr.hariprasadnaikbhattu]

Assura is available in Layout XL

[@anikarichie]

Thank you so much sir!!

[@dr.hariprasadnaikbhattu]

Thanks for the Support

[@kabandajamir9844]

So nice thanks sir

[@dr.hariprasadnaikbhattu]

Thanks 👍

[@mbabu9576]

Thank you sir

[@dr.hariprasadnaikbhattu]

You are welcome

[@dr.hariprasadnaikbhattu]

Welcome

[@mbabu9576]

@@dr.hariprasadnaikbhattu Hi sir how to estimate the area ? do we estimate area in schematic or in layout. please explain. thank you

[@rahulbhattu7661]

Thanks

[@dr.hariprasadnaikbhattu]

Welcome

[@BrindhaThanjavur]

Sir am doing for comparator circuit thats too big. I have some doubts. Can you share your mail id?

[@dr.hariprasadnaikbhattu]

How can I help you?

[@BrindhaThanjavur]

@@dr.hariprasadnaikbhattu My doubts are in layout sir. I am struggling how to do perfect layout. For me overlapping happens.

[@BrindhaThanjavur]

@@dr.hariprasadnaikbhattu i followed your 90nm inverter layout. While am trying for comparator in in 180nm i couldnt place vdd and vss as rails.

[@dr.hariprasadnaikbhattu]

@@BrindhaThanjavur madam you need to place vdd and vss in schematic also

[@BrindhaThanjavur]

@@dr.hariprasadnaikbhattu Yes sir i gave. I follwed your video only.While fixing rails it says other pins will go and it cannot be undone.

[@meghanaparusu9461]

Please help me sir

[@dr.hariprasadnaikbhattu]

I have replied

[@Praskand_Upadhyay]

psub stamp error mult

[@dr.hariprasadnaikbhattu]

Check the well dimensions

[@meghanaparusu9461]

Please help me sir

[@dr.hariprasadnaikbhattu]

I have replied