Designing a UART in VHDL.

[@berk6405]

Teşekkürler hocam

[@mustafaberkaysuer3401]

Yardımcı olabildiysem ne mutlu

[@stevetodd7383]

A quick thought for you. If you have a clock input that is a fixed multiple of your baud rate (say 8 times baud rate) then you can change baud rates by simply by changing the clock (for example by using an external counter and de-multiplexer). Secondly the number of stop bits can be an input, along with parity mode (none, odd or even, which your implementation lacks). The result will be a genuinely generic component.

[@mustafaberkaysuer3401]

Wow. Thank you for this comment. You are definetly right ,i will improve my design and I am sure it will be better for me as well

[@nhpt7143]

Usually I saw a UART board having a reset input. Why would not we include in this implementation? Thanks

[@mustafaberkaysuer3401]

I’m sorry for the delayed response, but I don’t use reset in my applications. However, reset should be included.

[@israeletu]

That's a good one there. But I have a little question please. What is the difference bewteen this implementation and implementation with microblaze? Does either of them have an advantage?

[@mustafaberkaysuer3401]

Excellent question and thank you. Both implementations are doing the same functionality, and from outside you can say that they are the same, but with this implementation you are going to spend less amount of resources ,and with a good design , you can achieve higher throughput.

[@israeletu]

Thank you very much for the answer. I appreciate.

[@stevetodd7383]

A second thought for you. If you intend to synthesise this into actual components (say on an FPGA or ASIC) then you should really be constraining integer ranges in your source code. If you constrain an integer to the range 0 to 15 for example then the compiler knows that it will only need 4 bits to store it. Likewise counting down to zero is more efficient as an all zero comparison needs less resources than a value comparison.

[@nhpt7143]

Do you know why we dont have any clock divider or baud generator implementation here? Also, I tried his project through his github code and I can not output the same waveform he has, actually the receiver does not receive

[@mustafaberkaysuer3401]

Thank you !!

[@pujiitasrieya9551]

Where did u add the three files in design or simulation sources u skipped this part can u say it?

[@mustafaberkaysuer3401]

I believe you are talking about Component instantiation. I just added another source file to my Uart_Demo project and created a component( It is the same UART project Ihave shown you before). Last thing i have done was instantiation. I labeled my components as UART_1 , UART_2 and then I assigned port map and generic map. After that my UART project became a sub-project of my UART_Demo project

[@SravanPuppala-n4x]

Can u add the complete code in description

[@mustafaberkaysuer3401]

I will update you when I open a github account.

[@mustafaberkaysuer3401]

github.com/mberkaysuer