Differences between Cache and Registers (Computer Architecture)

Check this video to know the differences between cache memory and registers!
Link to other videos:
1. Differences between SRAM and DRAM - • Differences Between SR...
2. RISC vs CISC - • RISC vs CISC | Compute...
3. Von Neumann vs Harvard Architecture - • Von Neumann Architectu...
4. Modified Harvard Architecture - • Modified Harvard Archi...
5. Von Neumann Bottleneck - • What is Von Neumann Bo...
Computer Architecture Playlist - tinyurl.com/22...
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#computerarchitecture #cache #coa #computermemory

[@BinaBhatt]

If you liked this video then check this one on the Differences between #SRAM and #DRAM - kzbin.info/www/bejne/jIXSi5h6aq2bpa8 Don't forget to subscribe and hit the bell icon!

[@guitaraditya6974]

This is the only video on youtube right now that explains the actual concept in such easy manner.

[@and1lnull]

Great video but that analogy at the end really brought it home ❤, I need things explained to me like a little baby sometimes 😂

[@smilebro9135]

Riyal

[@kellylang4456]

Thank you for this quick explanation. The analogy at the end was perfect.

[@keshavladha3244]

This was such an amazing video, the last 15 seconds of analogy summed up everything for me!! Thank you so much🙏🙏

[@tocabocafamilyklen2055]

Hi world!!. Always gets me 😂😂

[@stachowi]

This was fantastic. I'm an EE/CS... very clearly explained.

[@idkk403]

Excellent!!!!!!! No words literally!

[@BannableOffense...]

your explanation on the subject just gave me a way better understanding in the item I was struggling to fully understand, your awesome thank you!

[@genericYoutubeUser-to1zu]

very well explained and easy to understand. much better than other videos available on youtube

[@k283]

A cache should be larger than a register file (i.e. there are many more memory cells in the cache than there are registers, so the signal carrying address of requested cell is 1) longer (for example 16 bits instead of 4 bits) and 2) has to pass more logic gates, mainly multiplexers / demultiplexers, until the signal gets to its destination. Or maybe it has something to do with cache coherency? Let's say there is some hardware element that ensures coherency of different caches; then there should be times when the cache is locked, because coherency-ensuring element is updating the cache right now, so CPU has to wait until it's over, otherwise it would get incoherent data from the cache. Or the cache could be implemented with slower and cheaper technology; for example if the registers are built on Nand gates, and the cache is built on capacitors like DRAM. Though I think all CPU cache today is built with logic gates and not capacitors..

[@JennieMonroe-ge1td]

Thank you for your content

[@vibhu5034]

Great video with a very clear explanation, thankyou so much you are a great teacher.

[@girishmaitry8268]

Short video but very helpful🙂🙂

[@ctrltheory6070]

the analogy is perfect !

[@tomq6491]

clear concise informative thumbs up!

[@vishalgauswami2239]

Nice video Keep working on it. It's very helpful for others. Thanks.

[@AuroraLex]

0:45 This was the question I wanted answered

[@kunalsinghverma7883]

thankyou so much.. you made understanding easier .. 👍🙏

[@soukatdas9445]

as registers hold a lot amount of data and CPU can access it very fast thats why registers are better that cache

[@elisabetaronsson1730]

Thank you!

[@OneHypeMarketing]

very nice analogy! thanks!

[@tinnguyen199]

really helpful!! Thanks a lot😄

[@reinierkroneman5695]

You deserve credit for me passing Comptia a+ 🙏🏼

[@BinaBhatt]

That's very kind of you! Congratulations 👏

[@almirf3729]

Awesome, thanks!

[@user-ld8ru7kh6u]

Good analogy and explanation could u give the reaon why registers are ruicker to access compared to cpu cache? (other than physical distance)

[@jaron_yankey]

Great video!! Thank you!!

[@rsf2671]

I have Question about RISC.. There is a Difference between Risc and Risc-V??? Plzz Answer this. And make a vedio on Block Diagram of Risc-V.... Plzzz

[@jakubbbbbb]

Great video, thanks!

[@yusufetturki]

It was a great explanation

[@SunilKumar-ie2jh]

Wow very nice Video, thanks 👍

[@StudywithmeinPakistan]

Well done from Pakistan.

[@syedyousuffaizan1779]

Awsome content❤🔥🔥, very well explained. Would it be possible for you to make a similar video on how the data/address actually flow from the memory to cache and to the general purpose register, in detail?

[@dipan246]

Great content Thanks

[@reanwithkimleng]

❤❤❤❤

[@bitsandbinary5170]

nice mam.....good explanization

[@memoricadigitalschool101]

good explanation...

[@azazafridi689]

Bz the cache memory is highly storage as compare to Registers so its rule that in highly memory fetch data is hard as compared to low memory

[@BinaBhatt]

That's right!

[@akshaygodase8067]

Great video! But why internal cache is faster than external cache? Is this because, external bus to carry data is slower than internal bus? Like external is AHB where as internal is AXI?

[@msbanda2123]

👍

[@Cartoonworld-kr8op]

Regiter s close and small memory that is why fasr

[@nikhileshbajpai696]

So, when cpu requests data does it first checks in registers or in cache??

[@nikhileshbajpai696]

@@BinaBhatt Plze correct me if i am wrong, according to me registers will be accessed first and if data is not found then cache will be accessed.

[@BinaBhatt]

are you sure? You may want to understand how CPU executes programs in the first place.

[@nikhileshbajpai696]

@@BinaBhatt is it like the instruction which is currently being executed by the CPU the data related to that instruction will be stored in registers and if CPU wnats to access some new data it will access cache first.

[@Engineer884]

You didn't discuss whether register is fast or CPU cache

[@Engineer884]

@@BinaBhatt I'm not able to make any perfect judgement as both of them are on-chip near to CPU. If there's no hardware difference, then maybe both have speed. But at the same time, most of the places its written that registers are made of SRAMs which is also used to make Cache, and also written that register is faster than Cache.

[@Engineer884]

@@BinaBhatt please reply

[@Ind31181]

I'm studying for SSC CGL but getting nothing 😢