Digital Design and Computer Architecture - Lecture 15: Out-of-Order Execution (Spring 2023)

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@mikafoxx2717 9 ай бұрын

It's incredible that Robert Tomasulo came up with out-of-order execution and used in 1967 in the IBM 360/91, and then it was slept on for another decade or two until frequency scaling feom die shrinks wasnt enough, and you had enough transistors to make it. Much like the old 360/91. Slow clock but lots of transistors available..

@arifnishan5646 11 ай бұрын

What i learn: In out-of-order execution, instructions are not executed in the order in which they appear in the program or code sequence. Instead, the processor dynamically reorders and schedules instructions based on the availability of execution resources and the resolution of dependencies between instructions.

@이승섭-o2m 9 ай бұрын

감사합니다 잘 보고 갑니다 from korea

@vmscode 2 ай бұрын

01:16:06 after break

@Abhishekkumar-qj6hb 2 ай бұрын

@27.14 video the comparison of in-order vs out of order a minor error that needs modifcation: the MUL uses 4 cycles in first instruction and 5 cycle in fourth instruction so that is wrong, it should be 15 cycles vs 12 cycle , overall 3 cycle improvement , so please correct it in future lectures

@Rehan-Naeem Жыл бұрын

I slide 36, no. of execute cycles for MUL instuction is 8 not 6.

@АлишерХасен-к7ю 10 ай бұрын

how are you broadcasting simultaneously two finished execution?

@АлишерХасен-к7ю 10 ай бұрын

Didn't get, in hardware can we execute two instructions simultaneously? I am talking about stage after decode, I think we don't have a lot hardware to execute simultaneously? like two multiple or two adds ?

@secondclone33 Жыл бұрын

In slide 82, 'getting rid of replicated values 2'. In both RSs there are an additional V column compares to the 2022 version. You says they are for values, but I couldn't figure out what they are for. Can you please elaborate on that? Also, at decode/rename does 'allocate dest pr to dest reg' mean 'copy the physical register pointer of the current instruction destination to reservation station for broadcast after it complete'?

@OnurMutluLectures Жыл бұрын

A valid bit in the reservation stations indicate readiness of a value. They are needed for "wakeup" of instructions. Spring 2022 version omits these but it is better to include them (as we did in the Spring 2023 version) since an important function of reservation stations is to keep track of readiness of values and based on that to wake up and schedule ready instructions.

@chenyangzhou3084 Жыл бұрын

Hello, can I ask why we need the architectural register file and when to update it, just after retirement?

@АлишерХасен-к7ю 10 ай бұрын

And out of order execution we are literally changing order what about previous concepts of von Neiman from prev lecture, that each instruction should be after another without changing order? That it's hard to debug, we have some error, like division on 0, and when debugging we think that some instruction that after some potential errors instruction not executed but in real they already executed

@silentfox740 8 ай бұрын

Note the difference between Architectural Register, which state will not violate von Neiman principle of sequential instructions executing. Any changes which will appear in Architectural Register and be visible to programmer must follow same sequence, that high-level sequential code have. Same time, Physical and Future Registers may store results for operations which done speculatively. So there must no be problems with debugging. In case of exceptions/interrupts, any values which was used before exception must correspond to state in sequential model. Just ignore any values and instructions which was executed speculatively before being needed - they anyway must be invisible.