Digital Design & Comp. Arch. - Lecture 15b: OoO, DataFlow & LD/ST Handling (ETH Zürich, Spring 2020)

[@randomperson2815]

Please don't stop sharing these lectures regardless of how few people watch it. This is some rare high-quality content. Thank you.

[@douggale5962]

The end part is so true, many machines can hardly do one store per clock even though other parts of the machine have amazing levels of parallelism.

[@user-qf6yt3id3w]

These lectures are great!

[@AnuragNimonkar]

so is the clock cycle programmed for worst latency of the broadcast + capture + instruction wake up ? that could possibly mean updating N-1 cells of the reservation stations + M-1 tags of the register name table if all the younger instructions are dependent on the first. doesn't that make the clock cycle extremely wide or do you pipeline these stages as well?

[@rdxking411]

What is the state of prf after reset or at begining. Also how frontend and arf registers are mapped to prf at reset.

[@leoc0426]

Great content!