Digital Design & Computer Arch. - Lecture 6: Sequential Logic Design (ETH Zürich, Spring 2021)

[@isomane7911]

Watching your lectures while also reading and trying to solve exercises from Harris & Harris is an amazing way to learn computer architecture - whenever something isn't clear, I can find the answer in Harris & Harris and vice versa - if I don't understand some topic from book, lecture gives me the answer i'm looking for, thank you :)

[@samuelwawina2373]

Very good class, help me understand better what I could not grasp in the book. Just in the lecture video I would have liked to see where your laser pointer is pointing to, which would make it more comfortable to follow the details.

[@vxanica]

I think for Lecture 6, we cannot see the pointer of the lecture. A bit pitty

[@_gapry]

start at 3:59

[@isomane7911]

Could anyone explain how 4-bit d-flip-flop-based register at 1:10:22 contains 160+ transistors ? My method of counting was that every gated d-latch needs 18 transistors (4 nand x 4 transistors per nand + 2 transistors for one additional inverter) and then you have inverter for clock so that would be 18 * 8 + 2 = 146 transistors. What have I forgotten about ?

[@umutylmaz5174]

You haven't forgotten anything I think, 146 transistors should be just right.

[@zeshanahmednabin]

Can anyone tell me where the real CMU video of the right side is? I mean on which playlist and what is the title of that video? Because when he annotates on the right video. It doesn't appear on the left one. And it's difficult to understand

[@portport]

gm

[@muhammadhelmy5575]

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