8:30 Recap finishes 9:45 General CMOS Gate Structure 15:02 Latency 15:58 Power Consumption 21:36 Moore's Law 27:14 EUV 30:10 Combinational Logic Circuits 36:51 Boolean Algebra 44:08 DeMorgan's Law 47:57 Standardised Function Representations 56:56 Break 1:07:15 Sum Of Product recap 1:09:25 Product of Sum 1:17:47 Decoder 1:23:30 MUX 1:36:20 Full Adder 1:40:33 PLA
@mingyuhu9232 Жыл бұрын
Awesome😃
@mateusgodoy50608 ай бұрын
Professor Onur, I believe that on the 17th slide, the Dynamic Power Consumption formula has a 0.5 multiplying (C*Vcc*f), doesn't it? Thank you for all this wonderful knowledge shared!
@Inkarnid7 ай бұрын
The slide is correct. When you charge up a capacitor the power supply provides twice the amount of energy that is stored in the capacitor (which is probably why you think there should be a 0.5). When we are talking about power consumption we are referring to the total energy delivered by the supply over some time period. Because of this we have the power consumption as the energy multiplied by the clock frequency (in other words divided by the clock period).
@mateusgodoy50607 ай бұрын
@@Inkarnid Ooh I see, my apologies. Thank you for the explanation!
@achalpandeyy Жыл бұрын
At 1:38:12, I think Professor Onur Mutlu meant to say there are 7 AND gates, not 8, in the realization of the Full Adder. I think, the reason for this is because both carry_{i+1} and S_i have exactly one minterm in common (a_i b_i carry_i), so we reuse the corresponding AND gate for both the outputs, thus reducing the total number of AND gates required from 8 to 7. Consequently when you abstract it in a 3:8 decoder, I think, you will have to ignore, when finally OR-ing the decoder outputs, the output corresponding to (a_i = 0, b_i = 0, carry_i = 0) and reuse the decoder output corresponding to (a_i = 1, b_i = 1, carry_i = 1) for both the OR gates.
@Gr8ness89995 ай бұрын
in the logic multiplexers (III) slide shouldnt Y = AB*C+B*C* + A*BC (* means complement as i cant type it on the keyeboard)