Digital Design & Comp Arch - Lecture 5: Sequential Logic Design II & Hardware Description Languages

Digital Design and Computer Architecture, ETH Zürich, Spring 2023 safari.ethz.ch...
Lecture 5a: Sequential Logic Design II
Lecture 5b: Hardware Description Languages and Verilog
Lecturer: Professor Onur Mutlu (people.inf.eth...)
Date: March 9, 2023
Lecture 5a Slides (pptx): safari.ethz.ch...
Lecture 5a Slides (pdf): safari.ethz.ch...
Lecture 5b Slides (pptx): safari.ethz.ch...
Lecture 5b Slides (pdf): safari.ethz.ch...
Recommended Reading:
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Intelligent Architectures for Intelligent Computing Systems
people.inf.eth...
A Modern Primer on Processing in Memory
people.inf.eth...
RowHammer: A Retrospective
people.inf.eth...
RECOMMENDED LECTURE VIDEOS & PLAYLISTS:
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Computer Architecture Fall 2021 Lectures Playlist:
• Computer Architecture ...
Computer Architecture Fall 2022 Lectures Playlist:
• Computer Architecture ...
Digital Design and Computer Architecture Spring 2022 Livestream Lectures Playlist:
• Digital Design and Com...
Digital Design and Computer Architecture Spring 2021 Livestream Lectures Playlist:
• Onur Mutlu - Digital D...
Featured Lectures:
• Onur Mutlu - Supercomp...
Interview with Professor Onur Mutlu:
• Interview with Onur Mu...
The Story of RowHammer Lecture:
• The Story of Rowhammer...
Accelerating Genome Analysis Lecture:
• Accelerating Genome An...
Memory-Centric Computing Systems Tutorial at IEDM 2021:
• IEDM 2020 Tutorial: Me...
Intelligent Architectures for Intelligent Machines Lecture:
• Onur Mutlu - Invited T...
Computer Architecture Fall 2020 Lectures Playlist:
• Computer Architecture ...
Digital Design and Computer Architecture Spring 2020 Lectures Playlist:
• Digital Design & Compu...
Public Lectures by Onur Mutlu, Playlist:
• Onur Mutlu - Future Co...
Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:
• Lecture 1. Introductio...
Rethinking Memory System Design Lecture @stanfordonline :
• Stanford Seminar - Ret...

[@rojansfandoms]

Dear professor, I am a girl in Iran and with the protests I had no way of studying but your videos are really helping me. Thank you so much.

[@paulbird2772]

01:39 Sequential Logic recap 08:03 D Flip Flop Based Register 10:34 Finite State Machines 18:48 FSM State Transition Table 22:25 FSM Output Table 25:24 FSM Timing Diagram 30:40 FSM State Encoding 34:14 Moore vs. Mealy Machines 37:31 FSM Design Procedure 41:39 Break 52:35 Hardware Description Languages and Verilog 57:51 How to Deal With This Complexity? 1:01:28 Why Specialised Languages For Hardware? 1:04:32 Key Design Principle: Hierarchical Design 1:08:20 Defining a Module in Verilog 1:15:13 Structural (Gate Level) HDL 1:20:20 Behavioural HDL 1:26:24 Precedence of Operations in Verilog 1:32:03 What Happens with HDL Code? 1:38:53 Comparing Two Numbers

[@arifnishan5646]

More informative and clear explanation with real life examples. Thanx

[@willemhekman1788]

Awesome, makes me want to design digital circuits :-)

[@SherajusSalehin]

I wish I were a direct student of you. Your lectures are amazing, sir.

[@williamweiler236]

we have yellow in texas. we just dont have red and yellow at the same time (what you showed in an earlier lecture)

[@OnurMutluLectures]

Cool, thanks. My memory did not serve me perfectly well, perhaps.