Digital Design & Comp Arch - Lecture 6: Timing and Verification

Digital Design and Computer Architecture, ETH Zürich, Spring 2023 safari.ethz.ch...
Lecture 6a: Hardware Description Languages and Verilog II
Lecture 6b: Timing and Verification
Lecturer: Professor Onur Mutlu (people.inf.eth...)
Date: March 10, 2023
Lecture 6a Slides (pptx): safari.ethz.ch...
Lecture 6a Slides (pdf): safari.ethz.ch...
Lecture 6b Slides (pptx): safari.ethz.ch...
Lecture 6b Slides (pdf): safari.ethz.ch...
02:06 Recap: Why Specialised Languages for Hardware?
05:18 Implementing Sequential Logic Using Verilog
07:47 The 'always' Block
14:37 D Flip-Flop with Asynchronous Reset
23:00 Sequential or Conditional
27:33 Non-Blocking and Blocking Assignments
32:59 Rules for Signal Assignment
35:08 FSM Example 1: Divide the Clock Frequency by 3
39:16 Implementation of FSM Example 1
43:42 Break
54:51 Lecture 6b: Timing and Verification
56:51 Tradeoffs in Circuit Design
57:57 Circuit Timing
58:36 Part 1: Combinational Circuit Timing
1:06:31 Example Worst Case tpd
1:12:34 Output Glitches
1:15:53 Optional: Avoiding Glitches Using K-Maps
1:20:33 Part 2: Sequential Circuit Timing
1:24:21 Ensuring Correct Sequential Operation
1:29:46 Hold Time Constraint
1:33:15 Example: Timing Analysis
1:36:42 Clock Skew
Recommended Reading:
====================
Intelligent Architectures for Intelligent Computing Systems
people.inf.eth...
A Modern Primer on Processing in Memory
people.inf.eth...
RowHammer: A Retrospective
people.inf.eth...
RECOMMENDED LECTURE VIDEOS & PLAYLISTS:
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Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:
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[@paulbird2772]

02:06 Recap: Why Specialised Languages for Hardware? 05:18 Implementing Sequential Logic Using Verilog 07:47 The 'always' Block 14:37 D Flip-Flop with Asynchronous Reset 23:00 Sequential or Conditional 27:33 Non-Blocking and Blocking Assignments 32:59 Rules for Signal Assignment 35:08 FSM Example 1: Divide the Clock Frequency by 3 39:16 Implementation of FSM Example 1 43:42 Break 54:51 Lecture 6b: Timing and Verification 56:51 Tradeoffs in Circuit Design 57:57 Circuit Timing 58:36 Part 1: Combinational Circuit Timing 1:06:31 Example Worst Case tpd 1:12:34 Output Glitches 1:15:53 Optional: Avoiding Glitches Using K-Maps 1:20:33 Part 2: Sequential Circuit Timing 1:24:21 Ensuring Correct Sequential Operation 1:29:46 Hold Time Constraint 1:33:15 Example: Timing Analysis 1:36:42 Clock Skew

[@allocator7520]

these lectures are incredible 😬 omw to create a GPU from scratch :P

[@CyclopsOct]

On slide 52, it says combinational delay should be minimum for hold time satisfaction. Shouldn't it be maximum. On slide 69, tskew should be subtracted not added. Whether skew is postive or negative should be kept separate from the expression.

[@silentfox740]

@CyclopsOct, can agree with first point. But prefer to choose "long enough" (to keep contamination stage for Combinational Logic after circuit hold stage) instead "maximum". Professor even saying at 1:32:20, 01:35:45 that possible solution to satisfy "hold time" requirement for circuit is to make combinational logic longer. But 69 slide formula seems correct. In this example, if skew negative, you not care, because stable output from combinational logic part onto D2 will just remain for longer time. But if you have positive skew, it may shift unstable output from CL onto D2, before propagation of CL ended, and therefore, D2 will get unstable input during "setup time". What you mean by being kept separate from the expression?