DVD - Kahoot for Lecture 1: Introduction

[@tamilabhivlog9473]

Even single second not skipped in your videos, thanks beloved sir!

[@AdiTeman]

You're so welcome!

[@prabhanjanask6704]

This is fun!! Thank you so much for uploading these : )

[@AdiTeman]

Glad you are enjoying! I think it's also a good way to digest the material. I use them in class and I believe that they really work.

[@salandei]

@@AdiTeman I really enjoy your lectures. I'm a 1st year undergrad reading EE and want to go into the microprocessor design field after grad. These videos help a lot! Thanks!

[@tamilabhivlog9473]

Thanks for your videos and time sir ! 😇

[@AdiTeman]

You are welcome!

[@vevasam]

Thank you for the super informative lecture series. Just a quick question reg RTL. Even if the design is completely combinatorial, why would we still call it RTL design?

[@AdiTeman]

Funny observation. Indeed it is a bit weird to call a purely combinatorial design "RTL", but usually combinatorial models are only a small part of a larger design that also includes registers :)

[@veera-si8mg]

Thank you soo much Sir for providing informative videos and these are very helpful to us. Could you please tell me that anywhere these PPTs will be available?

[@AdiTeman]

Hi, The link isn't available, since the university has blocked access for IPs originating outside of Israel for security purposes. I have uploaded my lecture slide to a sharepoint drive in the meantime, so you can access them here: biu365-my.sharepoint.com/:f:/g/personal/temanad_biu_ac_il/EuORrTC7arlEn3S9M-0q2fEBd5DnUUiMIJ6DFd6cCPl4zw?e=aUktHb

[@veera-si8mg]

Thankyou very much Sir for your response.

[@vevasam]

A quick follow up question. The technology file contains standard cells specification. Aren't Standard Cell and Technology map file synonymous. Can you please clarify. Thank you.

[@AdiTeman]

So, I think you have a few terms mixed up. The "TechFile" (technology file) is actually usually a term used for the file that comes with the PDK for push-polygon layout (transistor-level) design. Essentially, you don't even need a TechFile to do physical implementation (for the most part). What we use for the backend flow is a "TechLEF" file, which is - I guess you could say - a reduced version of the TechFile in the LEF format that is used for place and route. It does not contain standard cells, though some standard cell libraries will provide the TechLEF, so you don't have to have the "analog" PDK to run place and route. Finally, we have the standard cell library. This is a collection of many files that describe the standard cells in a certain technology. They are, of course, built using the TechFile, but that is done by circuit designers and layout engineers. A full description of this is given in Lecture 3 of this series.

[@vevasam]

@@AdiTeman Thank you so much for a detailed explanation.

[@denisjoseph3665]

Why is there a need for a vendor to develop a std cell library, isnt the foundry more equipped to create a better library due to their process knowledge and generate more revenue for them.

[@AdiTeman]

Yes, this is actually the trend nowadays. Most fabs supply a library of standard cells along with the process, so they are both the fab and the library vendor. That being said, there is still a substantial amount of business left over for vendors (such as ARM and Synopsys) that design standard cell libraries and charge licensing/royalties for using them. These libraries either have some special specification that is different from the "generic" library provided by the foundry or they are better in some criterion because they are selling this as a product and put special effort into them. Sometimes they contain more cells with more functionality. But in general, the foundries do provide standard cells and many companies choose to use these.