VHDL Lecture 12 Lab4 - Process in VHDL in Explanation

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[@bryanchambers1964]

Really appreciate the slow and simple way you explain. Most comp sci teachers assume everyone is a computer genius and do the hardest stuff after two weeks.

[@bryanchambers1964]

First vid in series 114000 views, now only 7000. These subjects really weave out all but the most determined or talented (which I have none of).

[@ryanwwest]

These are great, high-quality lectures! Thanks for your time!

[@MaGra1959]

Great VHDL training - but this lectures has a very low resolution (max. 360) and is sometimes hard to read. Can you upload in 720p ?

[@EDUVANCE]

Sorry for the inconvenience. We will try to upload the upcoming videos in better resolution

[@manikanthnaidu3969]

CAN U PLZ SHARE THE SLIDES?

[@tchanabachir8254]

thanks a lot

[@fernandoluis53]

Great video but please use good quality video and speed up your videos

[@siriakkiraju]

I am using ISE 14.3 I have written the same code but my RTL and Tech Schematics are not same as those shown in this tutorial.The generated schematics are not wrong too as per the code.Why does that happen?

[@EDUVANCE]

The RTL and Technology schematic view generated after synthesis of description written in HDL looks similar if we click on both of them. However, if you need to see the difference between the two, you need to double-click on the block to see what hardware lies inside. This procedure is regardless of the version you are using.