EEVblog

Are power planes in a 4 layer PCB any good as a capacitor?
Can it work as one big bypass capacitor?
A look at an discussion on PCB layer stackups, and some measurements on 4 and 8 layer PCB power planes with different prepreg thicknesses and how well they work as a capacitor.
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[@steverobbins4872]

Nice video. I think the caps had sharp resonant peaks because of their low ESR. In other words, they have a high Q-factor. You can get rid of those sharp peaks by adding some resistance to damp it (lowering the Q). This is actually what bulk caps are often used for; people think that large caps are used on digital boards to provide a lot of low-freq filtering, but these caps are actually there for their ESR. For example, if you use a lot of 100nF ceramic caps all over your PCB you might see a really nasty resonant peak around 8-10 MHz. You could damp that by adding something like 0.2 Ohms in parallel, but that would obvliously waste a lot of power if you just connect a resistor from the supply rail to ground. So you dc-block the resistor with a large cap in series with it. Or, you just pick a large-value cap with some significant ESR, like an aluminium electrolytic. Anyway, I hope someone finds this useful.

[@shanekent249]

Nicely explained, Steve. Thanks a bunch!

[@w6wdh]

TDK makes their YNA18 series of surface-mount ceramic capacitors with controlled ESR values from 50 milliohms to 1.2 ohms. See Digi-Key for data sheets and available parts. I’ve used these capacitors and selected ones with 200 milliohms ESR for use as +3.3V and +1.8V power supply bypass capacitors. The controlled ESR gives very nice damping of transients. And the ESR of these parts is better controlled and more stable than the ESR of aluminum electrolytic capacitors, I think.

[@EEVblog]

Indeed. If you are in the business of having to add resistor dampening tweaks, you are in the serious end of town! General purpose Tantalums should have a nice flat curve like the power plane.

[@p_mouse8676]

Ferrites would also work.

[@zlac]

I use small ferrite bead (100-300 ohm@1MHz) together with 100nF for every chip on the board and a single 10uF ceramic as a "bulk" for the whole board just behind the voltage regulator (if it doesn't require "that much"). If microcontroller requires multiple 100nF caps, I use a single ferrite with 10uF as a bulk at programming pins, and then normal 100nF for each power entry point. I also use a 22uF - 100uF electrolytic before the regulator to prevent rush-in spikes and similar, seems to work very well. I up that to 330uF - 1000uF for automotive stuff because that stuff tends to have nasty spikes and long wires.

[@testep02]

I made a comment on the video about traps in chips and how those videos are the kind that hobbyists like me need. This another example. These videos are exactly the kind of info that you normally get when you work in the field for years. Because we hobbyists don't work in the field, and normal engineers don't share this info readily, videos like this are the only hope we have of gaining this info. Thanks so much for your efforts, Dave! It is TRULY appreciated by me and I'm sure thousands of others like me.

[@user-bp6mq5ed7l]

Nobody reads books, huh?

[@pretzelogic2689]

Had the opportunity to do this with a PCB on a previous job. There was zero bypass caps on the board. When I got the prototype for testing, fist thing was look at power. There was zero noise on 5V. I knew the thing was dead. Nope! It was working perfectly. Two 5v planes, 2 GND planes separated by an ultra thin dielectric. It works! Money saved was in the form of less time in component placement. Leaving off 200+ caps saves time.

[@juggernautforce]

Remembered a lecture where a sandwich was actually used as a supercapacitor. Mr. Agarwal from MIT made a very good argument of turning anything into an "abstraction" with an electrical equivalent (not just a cap.).

[@nicholasroos3627]

Funny how the subtitles read an aussie accented "nanofarads" as " dinner ferrets"

[@dotdissonance]

Such a great string of solid tech vids lately. Thanks!

[@CaptainDangeax]

I'm really curious to see the complete response after mounting all the decoupling capacitors on the whole board.

[@russgibson7376]

This was awesome! Thank you so much! I'd have really liked this a year ago when I was having issues ... but better now than never. In my case, the PCB was going into an automobile, and I had to fight hard to get them to use 4 layers rather than 2. Anyway the issue was there were 4 motors mounted very close to the PCB's, and the MCU was on a board perpendicular, and basically nothing I could do with the 2 layer board reduced the noise enough for the MCU to not act erratically. Started over from scratch with a 4 layer board, simply adding a +5V and GND plane's, and all was good. As for what I tried, it was everything from isolating the MCU with PCB cuts on 3 sides to leaving copper both under the MCU and on the opposite side (I "inherited" the original design ...), as well as power provided in a star configuration, and while I was able to reduce the noise by 2/3rds or so, it just wasn't enough (on the scope I'd see random noise spikes, especially, of course, when the motors were ran). Anyway, the 4 layer PCB combined with what I'd done before completely solved the issue. With several hours of (automated) testing, I never once recorded any noise spikes, with or without the motors running, even if I did the worst case of running all of them at the same time. 4 layers FTW! I now use 4 layers by default, and have to justify (per project) when to use a 2 layer rather than defaulting to 2 layer and justifying the 4 layer, as a direct result of this experience.

[@EEVblog]

Extra costs of 4 layer is pretty small these, unless you are talking mass consumer stuff.

[@pepe6666]

thanks dave this was one ripper of a video. i learned a lot about bypassing. im a huge fan of frequency plots these days & i got a real thrill out of this. on ya

[@Streamtronics]

learned a bunch here, thanks for your efforts!

[@EEVblog]

No problemo

[@thekaduu]

Good stuff as usual. Thanks Dave!

[@doughale1555]

As a young engineer, I designed inhouse testers. One was a hypot tester for PCB power planes. The tester put about 1500 volts across the planes. I tested one and left it on my desk. A couple hours later by boss picked it up and got zapped, I forgot to discharge it. I replaced the hypot power switch with a momentary button, when not pushed it puts a bleeder resistor across the planes.

[@reallyniceaudio]

amazing video!

[@electronic7979]

Useful video 👍👍

[@EE_fun]

There are books about PDNs from Eric Bogatin. He points out, that you can get rid of most of your bypass caps when using an ultra thin prepreg for power planes. Like 20-30um thin. He actually models this as a t-line instead of a cap. Pretty awesome. He shows how you can save hundreds of caps on a big digital Board.

[@p_mouse8676]

Good video Dave. One thing I would like to add is a ground plane (but power planes as well) can work as good shielding. Especially with a metal chassis this could be a reason to mount sensitive components on the bottom of the board.

[@BenBilesBB-box]

my 1st 4 layer audio boards didn't have ground planes at all ! it worked :) I always use them and bypass caps now! someone told me its possible power / gnd planes can act like antenna ? I think its more likely they would act as a shield for the signal traces , but I suppose there are so many factors depending what your actually building :)

[@Herby-1620]

A good experiment might be to take a piece of PCB (before etch), like the one you use for solder tests, and see how that curves out. See how they differ by board material, and copper weight (thickness). Then you can see just how they compare to the ideal formula you showed on this video. You don't even need to etch anything!

[@aikendrum1518]

Internal thin prepreg plane layers essential to reduce via inductance and fundamental part of the design of things like high speed CML transceiver ground planes like in some FPGAS. PCIE, SATA etc...

[@e74av]

Dave you rock...

[@Thefreakyfreek]

I used jlb pcb I'm impressed by the quality of the bord It looks so nice

[@EveryThingTechet]

Hi Dave, can you please post the link to your controlled impedance PCB video? Maybe update the same in the description.

[@PebblesChan]

Usable power plane capacitance performance kicks in at about 0.009in spacing (e.g. a 1/8inch 8 layer board) or closer.

[@waynethompson8416]

Hi Dave, I have a request of you. I have noticed on several circuit boards that the ground plane, instead of being a solid copper surface, it is broken up into a grid pattern. Would you do a video in which you explain WHY this is done, the advantages / disadvantages, etc.? I was once working on a board trying to figure out what could be done to resolve a problem we were having, and in the process I clipped the ground lead of a scope probe to the ground plane, and while thinking on the problem I was tapping the ground plane with the probe. Out of the corner of my eye I noticed something on the scope. At first I didn't see anything when I actually directed my attention to the scope, but then I happened to hit the ground plane again. There, clear as day, was a signal. It was a considerably large signal from one point to another of the ground plane itself! I suggested breaking the ground plane up into a grid pattern...thinking that might help...and was told I was an idiot. However, the very next run of circuit boards had the ground plane in the grid pattern....and the signal on ground plane issue was gone! I have since wondered if there would be significant difference if the ground plane had been made into circles instead of a grid pattern. Keep up the good work! Wayne WB4RHA

[@justobfuscate]

A couple of corrections here - The reason there's a more spread frequency response of the adjacent copper planes is because you are characterizing a distributed RLC network not a singular capacitor with a singular ESL which will show a distinct singular resonance characteristic. As for the useful capacitance found of 20nf? That is tiny! A single 0.1uf is 100nf! Lets say you have 50 of those 0.1uf caps distributed across the PCB - that's huge in comparison to the 20nf you find between the board layers.

[@OmarMekkawy]

I really liked this video. Its interesting, does the capacitance of the layers in the PCB change with the temperature and ruin your day if you have differential pairs or any high speed signal lines ?

[@gameoverwehaveeverypixelco1258]

Should do a video on those new solar panels made by Newcastle University.

[@guillep2k]

Dave, in my 4 layer boards I usually ask the manufacturers to place the planes (inner) close to the signal (outer) layers to help minimizing crosstalk between signals, as traces running together should couple more effectively to their nearest plane than to their neighboring traces. What do you think about it? My boards are usually low power, so loop inductance should be a lesser concern? How would you decide the trade-off in this case? Thanks!

[@CaptainDangeax]

Hi Dave. Does it also explain why, when you tested the removal of the decoupling capacitor, the capacitors had no inpact at all ?

[@dreamcat4]

Yeah Dave! Great video. Since were wondering what kind of uses you would find for this new and interesting piece of test equipment. Now here's my question: Can this tool be used to detect LCR resonances that generate COIL WHINE ??? It could be a great topic to cover, for demonstrating a real world and industry problem, which (even as of 2018), has still not been solved yet !!! And for the user / consumer, it can be a tremendous issue. At least for some of us. For example: Was trying to get a graphics card for my PC last summer. Bought a load of them from Amazon. But most of them had coil whine on my PC. 6 out of 9 of them. Had to keep returning card after card. It was a very painful experience. And in the end, the best of the bunch STILL had some coil whine under load conditions. It was simply less severe, being the least powerful device (GT 1030). And not nearly as good as the GTX 1080 I wanted to keep, went through 2 of those. And the problem can be even worse on the most expensive (top end) graphics cards, because they suck even more power, though the VRM. Some people say that it can occur due to a combined LCR resonance between the GPU and the PSU. When both devices are connected together (as they must be, to power the card). Some people even go to the lengths of recommending specific brands / models of PSUs. But there are also a whole bunch of other factors at play. And yeah... we are already talking about fully potted inductors here. But they still make the PCBs vibrate. Like a sounding board. There are also other information sources for researching this topic. I can dig them out if necessary, if it comes to that. An obstacle for generating content on this - is getting some test samples (GPU + PSU). Which actually exhibit this issue. So it can be reproduced easily. There already 1-2 people I can think of (in your country) who might be interested to help you. Who are fellow youtubers, other channels, who are already known to like and enjoy making collaborative content when its relevant / makes sense. One of them is 'Hardware Unboxed'. However they are based some distance away in Melbourne (not Sydney). There is also 'Tech Yes City'. The 'Yes man' - also has a suitable pool of computer hardware to draw from. And again, is somewhat knowledgable about these things. At least from a consumer perspective. Again, Yes man is based somewhere else in Aus (this time - Brisbane). I suppose there might be other more convenient sources of computer hardware. That are more local to you. This topic also raises other questions for me. For example: And how can we better help the industry to solve this problem, for us the customers? And how do the manufacturers of these devices test their own products? What is their QC system like? We are talking about manufacturers such as MSI / ASUS / EVGA / Gigabyte.

[@michelfeinstein]

Dave, have you read "Electromagnetic Compatibility Engineering" by Henry Ott? There's a great chapter analyzing parallel capacitors for decoupling. In case you didn't, I can send the chapter to you.

[@protonjinx]

Would have been interesting to see the curve of combined capacitors on top of just the singles.

[@graywolf2600]

Which video did Dave do on "controlled impedance"

[@T3sl4]

I'm impressed that the planes are as lossy as they are. A good illustration of how /bad/ FR-4 is as a capacitor (definitely not good as said at 16:27 !). Good /for purposes of damping the supply/, however. 24:40 have you calculated what the spreading inductance is? (Say for a via connection.) The formula is fairly easy to solve; the result is embarrassingly small for most plane sizes. Via length completely dominates. Via length /plus body length/ completely dominates for a chip capacitor, so it is rather disingenuous to say that a tiny "1 nano" can do better than a plane. The graph at 26:03 proves that that document isn't much of a reference: notice the impedance peaks do not rise above the impedance intersections. This is very misleading, a trap not just for "young players" but old ones as well! The ESR and C form a parallel resonance, which peak above the lines the same distance the series-resonant valleys peak below. Cheers!

[@DrakkarCalethiel]

Good morning everyone! (5:13 AM here in Austria)

[@Sheevlord]

6:15 in Latvia and I've been up all night like an idiot :D

[@DrakkarCalethiel]

Priviledgier Shitlord Same. Was soldering, etching, polishing cutting and gluing the whole night. Definetly going to bed after this vid. :D

[@josuelservin2409]

10:30 PM Here in Mexico, have a nice rest!

[@lunarlancer]

9:31pm here in Alberta Canada

[@cr6925]

Morning! 4:38am here in the Forest of Dean, Gloucestershire, UK 😊

[@jonathanfadden9299]

DAVE, If we want to reduce EMF, why not put the traces on the middle layers and power planes on the top and the bottom for shielding?

[@magnuswootton7368]

You could use this board as a ram chip - if u keep scooting through side to side.

[@SugarBeetMC]

7:30 That board is like, one micromile thick.

[@natecontarino1748]

That is so nerd cool.

[@petersage5157]

I think it would have been interesting to see a plot of a typical bypass capacitor in parallel with a ground plane. Would the peak be better or worse than the bypass cap alone? (Could this be investigated with "design by inspection"?)

[@henricoderre]

Where did you get that electromagnetic chart behind you in this video?

[@electronicshobbyistmushtha5448]

What is that tool.?

[@izimsi]

Can I get a single better quality prepreg for high frequency stuff, and fr4 for the rest?

[@user-bp6mq5ed7l]

Yes, of course.

[@electronicsNmore]

I'm amazed that you were able to get (4) multi-layer boards for that price.

[@Necrocidal]

JLC does 5x impedance-controlled 4-layer for $2 now (

[@OmarMekkawy]

Its like a joke, its EEVblog #1117 and there is LM1117 LDO :D :D

[@ahbushnell1]

The deep dip is low ESR. Looks like the PCB has high ESR. Might be the wire. Does the cal take out the lead resistance? ESR maybe skin depth.

[@icestormfr]

Also the low resonance frequency indicates an inductance in the 100nH range (wire inductance) When using two flying wires the calibration is not easy/reliable as you shouldn't change the transmission line properties (e.g. loop area/distance between both wires)... Using a twisted pair or coax would be more trustworthy/reliable.

[@ahbushnell1]

I agree. A PC board inductance at the terminals will be low. there will transmission line waves bouncing around but that would be in the 100's of MHz depending on the size of the board.

[@martinhorodrigues5511]

hi! how are you? my name is Martinho and I live in Brazil, in São Paulo city, i see a lot of yours videos in youtube, congratulations they are great!!! I want to know how can i buy one of those EEVblog multimeters. best regards and bob is your uncle!!

[@Mel-vy1zm]

Hello I'm a student I want to learn where to put decoupling cap in a multiple chip? Thanks

[@Agent24Electronics]

Oooh, look, I'm big!

[@electronicshobbyistmushtha5448]

😍😍😍

[@Audio_Simon]

EEVblog Please consider making a video on regulator design and implementation. Especially how to use LM317 such as adding a zener or LED as low Z current source or combining with a capacitance multiplier pre-reg and pass transistor etc.. This would surely be of use to many people.

[@petersage5157]

The impression I got from your Muntzing video was that you were having these made up with power planes specifically to check their distributed capacitance. There ain't no rule says the signal layers have to be top and bottom and the power planes on the inside, is there? Couldn't you, for instance, place the power and ground planes on one side of the core and the signal layers on the other side?

[@danmills7613]

that can get tricky because you usually want more or less equal copper weight on both sides of the board to reduce the things tendency to warp, I had some right banana RF boards before I figured out what was going on (Two layers, solid plane on the back, just the RF and power on the front).

[@petersage5157]

Ah yes, I'd forgotten about the warping issue; that's a good point. How'd you fix that on your RF boards? Crosshatched plane? Anyway, I'm just an AF guy playing around with FETs with pilot lights; if I need to add local bypass, it'll usually be a C0G ceramic disc directly across a plate resistor to the local B+ (because the plate resistor goes to the local B+ and redundancy is fun because redundancy). Only slightly related, but I managed to accidentally taco a bicycle wheel once because the spoke tension was a bit out of whack...rim was ruler-flat until I hit a little speed bump.

[@olipito]

Why is it cool to have capacitance with the layers?

[@jeremyvenin6813]

I m interested to have the answer as well...

[@jeremyvenin6813]

Oh yeah makes sense that's clever ! Thanks :)

[@pranit9668]

I'm all the way __ 11:45.... Nothing can stop me, I'm all the way __ 11:46

[@michelfeinstein]

Just a tiny trap for young players, depending on your parallel plate capacitor size, the fringe fields from the edges can make the true capacitance be the double of what the approximation formula gives you.

[@Wren6991]

A common approximation is to add the separation to the width to get effective width with fringe fields :)

[@Wildcats1266]

Dave doesn't blink..

[@MatthewSuffidy]

At 5:00 I thought you said the copper should not go to the edge so when the board for example could hit the chassis, it would not short out? I guess ground is not necessarily a bad thing to short out? Maybe we are just seeing the fiberglass edges here? OK maybe you cut out a bit to do this. So I am a bit confused, the point was you changed a 2 layer board to a 4 layer board to make it smaller? And then the extra capacitance of the ground planes doesn't really effect the logic?

[@EEVblog]

I ground away the board to reveal the inside copper, it normally has a pullback form the edge.

[@OwNdWire]

This Is Space

[@Mtaalas]

19 hours ago... why the hell doesn't KZbin show this on my feed... F YOU KZbin! I subscribe to channels to see _EVERY SINGLE VIDEO_... and preferably right now!!!! Krhm... sorry about that... rage kind a took me over there. Thank you for the video! :D

[@ahbushnell1]

plot a series RLC (R+jwL+1/(j*w*C) and change the R.

[@23RaySan]

and how are you are going to muntz this thing? ripping the ground plane out? ;-)

[@synthead]

Great, now audiophiles will replace the ceramic capacitors in their amplifiers with unpopulated PCBs 😂

[@mcconkeyb]

:-)

[@gunlimitedammo3888]

Oh Christ how horrifying

[@schitlipz]

I'm too hungover to watch 30 minutes of KZbin. What are the answers to: _"Are power planes in a 4 layer PCB any good as a capacitor? Can it work as one big bypass capacitor?"_

[@rogeronslow1498]

No pain no gain.

[@PebblesChan]

Usable power plane capacitance performance kicks in at about 0.009in spacing (e.g. a 1/8inch 8 layer board) or closer.