EEVblog

Eagle eyed viewers spotted a short between two pins on a TQFP chip in the previous teardown video. This isn't a dodgy assembly issue, it's a deliberate design short, Dave explains how and why.
Solder masks and snap grids.
3 Ways to FAIL to PCB Manufacturing: • EEVblog #1327 - 3 Ways...
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#PCBdesign #Manufacture #Soldering

[@BeatRush2011]

TL;DW: Laziness by the PCB designer in this case but useful sometimes when space is tight ;) And much great information in this video, thanks!

[@thenoisyelectron]

Whenever I come across solder bridges, I play a disney themed princess song and say those pins were meant to be together

[@thenoisyelectron]

@@averageemogirl but in love stories, opposites attract! Also magnets

[@DavePoo]

Those pins finish each others sandwiches

[@stuartmcconnachie]

You know just sometimes you just have to let some things go....

[@oskimac]

I was expecting a pinout of that chip and some explanation of why they are shorted. But ended learning more

[@scottlarson1548]

Don't *ever* expect Dave to give a simple explanation for anything.

[@rbmk__1000]

I love the bromance between louis, dave and clive

[@gustavlicht9620]

Dave, you have been recording for many years now. New people are coming to the trade, and they may not have seen all your videos. You are so prolific that I myself won't have time to watch all your videos. Anyway, I have learned something new. I work mostly with DSP and communication and this was really something new to me

[@modelrogers.19]

You are incredible taking extra time for *us*. The world is changing. Thank you again!

[@mikemike7001]

Makes me wish I had a PCB to design. Always love the challenge of working in both imperial and metric and aligning everything to multiple snap grids - not. Gotta love pad snap though. Adjacent ground pins seemed obvious to me, but as always you go the extra mile and throw in a ton of useful related info and even a physical demonstration. Really appreciate all the hard work you put into every video. Always fun and informative.

[@pete3897]

It's time to build yourself an audio-triggered "ON AIR" light for the studio which is tapped to an immutable output from your main editing machine ;-)

[@juddfoster8555]

12:24 they actually can manufacture this part, check the minimum trace width and pad to pad clearance section. You just won't be able to get solder mask between the pins.

[@southwestelectronics4902]

I feel like i got a waaay better education from you than if i finished my EE degree. Thank you so much !!

[@FIXDIY]

Thanks, I am always confused about distinguishing between the wrong shorts and the fabricated shorts, and the solution that you suggested is a good one.

[@piwex69]

I was waiting for you to take the reference for this chip and show us the sense of this bridge. If it is deliberate, it must have a purpose...

[@superjimnz]

That's still really poor form; it's a nightmare for anyone inspecting the board and for AOI. Better to do it like the two pins on the opposite side.

[@PaulTheFox1988]

I know most people who watch these videos will already know this, and most are far more knowledgeable than myself but for those who don't know here's a brief explanation of why it's done. Some of the reasons they might have deliberate solder bridges is because a pin might need pulling high or low to prevent floating i/o pins or because those pins need pulling down to ground or up to 3.3v or 5v etc in order for that chip to work, and rather than routing entire traces for that purpose you might as well just reuse existing pads.

[@Aerospace02]

I'm a PCB Design Engineer in the automotive industry. Our design rules don't allow us to short pins directly between pads like that. This is due to the Automatic Optical Inspection process at the plant flagging it as a solder bridge.

[@xDevscom_EE]

I don't like doing that way shorts on PCB as it adds additional "explaining" for QC/QA people that it's not a assembly problem, but deliberate short. Just makes it easy to do traditional short outside of fanout pads, just like Dave mentions at 18min :)

[@EEVblog]

It took me 18min, but I got there :-D

[@ptamog]

I've been there. Now I avoid them

[@Graham_Wideman]

"Solder mask expansion" actually means "solder mask reduction". Or "solder mask _opening_ expansion". [Edited to add...] Or "solder mask clearance from pad", which is further helpful in that it suggests not just the direction of the deviation, but also a rationale.

[@Iceberg86300]

Yeah, that took me a bit to realize

[@edwardfanboy]

I think it's phrased like that because of how boards are normally designed: The design files for solder mask layers don't specifiy where the solder mask should be placed, they specify where it should be excluded from.

[@Graham_Wideman]

@@edwardfanboy I agree with your assessment. And every discipline has terminology that's come unmoored from its original full wording, and the most corrosive instances are where the term means the reverse of the literal meaning of the words. I'm pushing back. As design of the solder mask is by specifying where the mask should be excluded, then "expansion" is of the exclusion region, not of the mask. So: "solder mask exclusion expansion" then, or "solder mask clearance from pad". I think it's especially important in a discussion that's specifically intended to introduce the topic to viewers who don't already know the material.

[@moddquad8362]

0.2mm snap grid for holes 'rules them all' when using a 3D printer to make a pogo pin harness.

[@vasiliynkudryavtsev]

Usually, people who do assembly and designers are not the same. The assembly company I used has a strict rule for this case: short must not be in center(H) but should be on the outer side of the pads(П).

[@Spoco]

Having used to test and fix boards at a factory one time, I would've probably thought that was a short. Most boards that didn't pass the tests had either solder missing or a short somewhere. Even after manual visual inspections upstream. Then again because we would handle like thousands of identical boards a month, you would quickly make note of that.

[@ChipGuy]

I don't short 2 TQPF pads like that in the middle anymore. Always under the solder mask. So the rule for inspection is easy: If the inspector or the AOI sees a bridge, it is a failure. Modern AOIs have training templates for that.

[@leonerduk]

As Dave says around 18:30 onwards; it's best to avoid these when possible. I don't like doing them precisely because it confuses visual inspection later on. Even if it's supposed to be there, people will forget that - or even you ship it to the customer and they complain afterwards. For avoiding doubt it's easiest just to avoid these things, and route the copper elsewhere where it looks deliberate.

[@UpcycleElectronics]

Hey Dave, I just finished retracing the Nintendo Game and Watch. While working on it someone gave me xrays of the board, a first for me. The xrays didn't actually help with the trace due to quality issues in critical areas, but I did notice a large number of internal traces had internal ground traces routed in parallel to them. This was in addition to a bottom ground plane that was only broken by the carbon contact button pads, and a well stitched and layed out top ground fill. The micro has a max frequency of 280MHz. There's no analog. It has a TI BQ24072 for lithium battery management, a mystery bga switching from 3.7 to 1.8V, a 3v3 linear reg for the LCD, a 1MB 108MHz SPI Flash, and a mystery bga audio amp. There are a few transistors and passives, but that's it, nothing fancy. The extra parallel internal ground traces made the routing a good bit larger than I first expected before seeing the xrays. What's the deal? When where and why, I needs to know :-)

[@keeperofthegood]

18:54 vrrrrr Yes Dave yes, it sounds just like that. Ask your son Im SURE he would agree :) vrrrrr yup that is the sound of conveyor belts everywhere!!

[@Veptis]

I don't know much about EE, but still watched. Finding where a pin is bridges go ground is the single most question I have that is holding me back from achieving my dream of having a thermal camera. But serial read is grounded. The camera doesn't hear me.

[@St0RM33]

JLC removes the solder mask manually from the package footprints they can't manufacture; yes they didn't put a rule for this but the board is done fine after they fix it themselves :)

[@timjackson3954]

I had a prototype made at JLC recently where I didn't set the mask clearance. They didn't reject it, just went ahead and made it with the pad overlap. Lost about 30% of the usable pad width on the QFP. Which was no problem for my hand-soldered prototype, the board worked just fine.

[@justinlynn]

Super seriously wish the designer would've put a silkscreen note: "bridge pins" with an arrow.

[@EEVblog]

If you have space for that you liekly have space to route :->

[@zeitgeist909]

@@EEVblog which the designer did neither! he had space for a silkscreen note AND to route - but choose the short... we need to track this guy down and ask him WTAF?

[@treelineresearch3387]

@@zeitgeist909 I've done this on at least one of my boards and never even considered that people would find it puzzling. If you're that deep into looking at the board I'd expect you to have the chip datasheet and see it's just a couple ground pins bridged.

[@elfujo6595]

Or more fitting “bridge pins” with a question mark.

[@vasiliynkudryavtsev]

Before I've done assembly of my board, I had the same mindset. Like one can check the top/bottom layout during assembly. The truth is the very assembly and reflow processes have so many gotchas, that making more problems intentionally is bad practice. I wish there would be "check-your-style" automated design rules and warnings for these cases.

[@wafiullah-shafia]

Thank you for this video Please which program application you use for video production ?

[@carldurrell9943]

Great video I missed you mentioning this in your other videos, and found this really helpful and will learn from it, so I know in future if I see this that it is deliberate and not a short.👍⚡️

[@CaseyConnor]

Can someone help me understand what the solder mask presence/absence has to do with it? I understand the point of a deliberate short between pins, and everything about the manufacturer tolerances and so forth, but not why the absence of solder mask between pins would be a clue that such a short was intentional. If you had solder mask between the pins, you could just as easily plan an intentionally-routed short between the pins, no? If anything, the lack of solder mask between the pins would make the diagnosis of an accidental short more likely, not less, no?

[@jrb_sland5066]

I've often shorted two side-by-side port pins together to get a bit more output drive current into an unusually low-resistance load. Need to annotate this hardware fact carefully in the software listing, and it only works if the second pin is not used for something else. Software must toggle the state of both pins simultaneously, of course.

[@romanherrera1794]

Recommended solder mask offset is 0.075mm for fine pitch less than 0.5mm pitch or If it cannot keep A≧0.125 B≧0.075 (C＜0.275), surround whole pins with solder mask.

[@philiplishman532]

On a project I have to hand solder a 24pin 0.1mm pin pitch flat flex connector. In earlier revisions I had a 3v3 line going into two adjacent pins bridged between the pins, but I found this caused a larger volume of solder to bead on/between those two pins than the others, enough in some cases to wick up into the back of the connector and to adjacent pins. TLDR: Maybe easier for you if you don't do it when you need to hand solder small pin pitch devices.

[@leviathanx0815]

We once did this by design for an input signal based off a frequency. It was done on two interrupt-capable pins. One would be configured to fire for high to low (falling) and the other low to high (rising). Yes, it was a chip with no dedicated IOC unit. So you gotta work around limitations and live by a compromise (that is, some jitter due to ISR handling).

[@KillerSpud]

I just leaned what "Chuck a wobbly" means. I love it.

[@willynebula6193]

Lol made me laugh

[@nukular2008]

I recommend watching the "Guess the Aussie slang" videos by Ozzy Man here on KZbin. They are quite funny and you will learn new words that Dave also uses sometimes :D

[@robbieaussievic]

...... And I don't think anyone under 30 would get the 'Gone Birko' either.

[@sikkepossu]

Well what those mean then? "Chuck a wobbly" and 'Gone Birko'?

[@robbieaussievic]

@@sikkepossu www.australiaday.com.au/get-involved/aussie-slang-dictionary/letter/b/

[@jameslmorehead]

As an electronic technician who hand solders and inspects prototype PCBs nearly daily, I can say without a doubt, I HATE traces bridging pads. Without having the PCB layout files printed, or spare boards to look at, I don't know if it's an intended bridge or not. IMO, it's a very bad design for prototyping. Find the space and run the trace under the solder mask. It saves so much time for technicians and only takes a minute or two for an engineer.

[@Joe_HamRadioGuy]

Nice explanation video was just fine thank you for taking the time to teach us.

[@SurmaSampo]

Pin shorts are also sometimes used to enable and disable IC features for whatever reason.

[@russgibson7376]

In the last couple of PCB's I've done, I actually used a small copper pour to encapsulate the two pins next to each other. The pour is from 1/2 way between the middles of the pins, and all the way to the external area. I haven't decided if I like it or not, but in the case I originally used it for there were 4 pins next to each other that were all ground, and the datasheet was adamant that there be plenty of flow and as little impedance as possible for the pins. It worked well, and in fact resolved an issue that the original designer couldn't resolve, but I'm not sure I should have done it that way by default now (as I have kind of done).

[@thomhpl]

Another issue with a bridge like isn't that the bridge will actually suck up some of the solder paste and therefore could cause the pins to not have a good joint?

[@Aethelbeorn]

21:00 Keep wafflin' on, mate!

[@enilenis]

I have an old 486 Gainbery Maximizer CPU that never worked. One day I noticed bridged pins. I thought that maybe someone was overclocking the CPU and maybe those melted due to heat. I removed them. They were positioned higher up the chip and weren't right on the PCB. I did not record the position of bridged pins. I then discovered that the CPU itself was bad. I got a replacement, which is a huge SMD job with a fine pitch. But the issue is that I did not record positions for the bridged pins, before I removed solder, so I'm no longer sure which pins were closed. I found photos of a Cyrix CPU that has bridged pins, but I do not know if my AMD variation had those bridges in the same places and whether there was the same number of them. I'm now stuck.

[@rtos]

Adding solder mask between pads could result in misalignment of the mask and it moving onto the pad area. Tolerance becomes much tighter and slight registation issue of the solder mask layer could make the soldering of smd package difficult.

[@user-marco-S]

In a previous job of me, we did also have pcb's with a deliberate short as on the pcb you showed under the microscope. We also had pcb's without solder mask, but these got a special coating on the end (making replacing a pine-pitch ic very difficult).

[@paulpaulzadeh6172]

if you look closely again pin 8 and 9 are short out of solder mask ( this is the right way ) but if you put that short in the middle of pin center , then looks short ( which is actually is wrong way to do it in layout ) , in my layout i never do it like that , if pins are short i take it out little bit to solder mask , in this way in can be easy for inspection

[@SverigeKodar]

That's unfair to JLCPCB. The soldermask expansion of 0.05mm was not a requirement, but a recommendation. If you where to actually read the information it did not say "must", it said "should". I've had pcb manufactured by JLC with less than 0.05mm expansion without issue. They only recommand 0.05mm as that is the minimum alignment they can guarantee, but it's usually much better than that.

[@goamarty]

at work we are supposed to avoid such shorts between pins. We have soldermask there anyway. But the AOI would become confused. So we should make wanted shorts not directly between the pins and at the PCB review somebody would complain otherwise.

[@k4be.]

We always avoid to connect pins directly to avoid these connections looking as a short. This makes service people life easier.

[@McTroyd]

This really threw me for a loop on, of all things, a cheap clock kit from eBay. I've soldered for a long time, but this was my first real shot at surface mount soldering. Got all the resistors, caps, and LEDs in. Feeling emboldened, I started soldering the real time clock IC. It's a 16-pin SOIC package, and instantly, pins 5-8 and 9-12 bridged. Figuring it was my own ham-handedness, I wicked away the solder and tried again -- and bridged it again. This back-and-forth continued until I literally destroyed the IC pulling it off the board. At that instant, I saw those pads had all been bridged on the PCB. Dug up the datasheet, and it turns out this clock IC doesn't use those pins for anything... it normally comes as an 8-pin SOIC, and the remaining pins are shown as no connection. The board designer shorted them all together, as you showed. D'OH! 🤦‍♂️🤷‍♂️💥

[@jrb_sland5066]

I always solder the chips first, before the smaller parts. Depending on the layout, you may have trouble doing a drag solder along a row of pins if there are small resistors/capacitors very close to the chip, as is often the case in my designs.

[@McTroyd]

@@jrb_sland5066 Next time I plan to do exactly that. Make damn sure to check the pads too. 🤣

[@marcdraco2189]

The wicked Ozzy sayings got me to subscribe. I'll learn the PCB design while I laugh!

[@punpck]

11:00 I ordered most of my PCBs with solder-mask expansion of 0 and jlcpcb didn't complain. Afaik they don't really care about - they adjust it automatically to what they are capable of. Always had little soldermask bridges between the legs of my 0.5mm QFPs what actually wouldn't be possible if using an expansion of 0,05mm. But I also order my stencils always reduced by 10% - so this could be the reason why after soldering I don't have problems with solder paste on my pads with zero expansion^^

[@marksandlin8376]

I try not to make connections between pads like the example. I've had assemblers try to fix what was perceived as a defect and damaged the board in the process. Seeing the connection that was being made, I would probably have done the same thing. There is always a trade-off between the ideal layout and what you can do in the space you have that has the least chance of causing problems when the board is made.

[@robertsmiczsmiczamplificat593]

Even the second time was perfect. Perfectly explained. Good on you mate!

[@robertsmiczsmiczamplificat593]

Tighter then a nuns nasty is going to be my bands new name. Its perfect! I can see the Marquee “Tighter then a nuns nasty” previously known as “My Dixie Wrecked” playing live tonight. With special guests “liquor up front” and “poker in the rear”! Sorry. I know, childish, but i love the saying Dave, its much better then the standard, its smaller then a blonde C hair. lol!

[@darkwinter6028]

I’ve done that myself when two pins need to be shorted; usually when some configuration pin needs to be held high or low and it’s either next to the appropriate Vcc or Gnd or some other configuration pin that’s also being held high or low.

[@adamlong1445]

At 1:35, check out the short between pins on the middle of the bottom side of the IC. It is done so it with a copper track such that it doesn't look like an accident.

[@johnyang799]

Could you make another video about circuit studio? Is it more stable than Altium?

[@LaserFur]

I would have brought out the trace so that soldermask keeps the traces isolated. I have done this on several products since many of these processors don't let you monitor pins that are connected to Uarts and stuff. So you have to connect to two pins. I also connect the "erase" pin to a I/O pin so I can have the program erase itself when it hears a special command on the serial port. And for pins with a pour I have to go in and add keepout to prevent it from automatically connecting them like this.

[@eduardvoiculescu975]

20:21 the designer did a proper tie on two pins on the bottom row. That upper one is for sure a bad solder bridge.

[@EzeePosseTV]

"Tight as a Nuns Nasty" Haven't heard that in a long time. It was a nasty _Habit._

[@honzakratochvil]

Pinout -> i.imgur.com/1mVydQ7.png Another shorted pins "by design" -> i.imgur.com/B7m7Jno.png This is obvious, they are shorted under the solder mask. Anyway, shorted pins RD3 & RD4 makes no sense. Maybe to drive (sink/source) higher current than 25mA ?

[@LorneChrones]

My guess (assuming those two pins are set as outputs) is to double the drive strength. MCUs back then had relatively crap drive strength compared to MCUs within the last 5-10 years. Or perhaps if both are an input perhaps it's overloading that net for two separate special functions on the MCU that are tied to those particular two pins (e.g. timer start, interrupt, etc). Third possibility, its a bit banged or hardware 1-wire serial line.

[@onlyrgu]

Beware of solder masks, sometimes they don't exist as you see in the CAD, it can be really problematic if you have small pads.. I had a nightmare with DSBGA package an year ago. I had to X Ray to find the unintentional shorts under the IC

[@imir8atu321]

Well done, Video was a wonderful fallow up. I missed the bridge on the previously video also enjoyed👌 proved You have an alert subscribers.👍

[@niw3]

They did specify the minimum solder mask thickness. It says 10-15 um on the page you show.

[@tricky778]

How does one probe pins at 0.40mm pitch on an lqfp chip?

[@sergeantseven4240]

JLC usually does pretty good with alignment on my boards when I do QFN packages...

[@StreuB1]

I absolutely love videos like this. As a mechanical designer who wants to start learning this stuff, this is invaluable. Thanks Dave!!! And WTF "Chuck a wobbly" HAHAHAHAH!!!!! Thank god for Urban Dictionary!!!

[@EEVblog]

I don't recal throwing a wobbly into that video!?

[@StreuB1]

@@EEVblog nah, you used the term. I was like "WTF does that mean?!?" Had to look it up. Hilarious mental image. 🤣🤣🤣🤣🤣

[@tibfulv]

I first came across snap grids in 1995, with Xfig.

[@artursmihelsons415]

This bridge was pretty small. One time I see big solder blub between pins after someone else messed with board and didn't find fault.. Removed that blub and no traces under, no short anymore, but circuit start acting worse.. Googled out images from that board - yeah, all boards have this blub.. That's mean, pcb designer forget to put bridge between traces and blub was added later in manufacturing process after troubleshooting.. :D

[@tonybell1597]

Thanks Dave...... its the smallest of things... but easy to get bogged down on a fault if you didnt know about this stuff.... cheers...

[@jackykoning]

JLC did not care with my 0mm solder mask opening.

[@randomname3894]

Yes, I’m always setting it to almost zero, they’ll adjust it. Elecrow does it too.

[@TheChrisey]

I handsoldered a 144pin ARM chip with a 0.2mm pin pitch without any soldermask whatsoever, not a single short ;)

[@victortitov1740]

Snap grids is something i'm starting to passionately hate, after I have tasted topological routing, and constraint-based design in mechanical cads. Grid is quite convenient when all components align nicely to it. But as soon as you have some mix of different pin pitches, grids become a pain in the ass.

[@mikemike7001]

Exactly!

[@gunnark9823]

I think there is too much solder on it, therefore everyone would think it is not the intention to bridge the pins. Look on the left side, there are real solder bubbles.. Even when soldering this manually, you will use much enough flux stuff to get rid of those bridges, even without a soldering mask. It was made really bad imo ;)

[@gusbert]

Our PCB design guidelines forbid connecting pads like this for the very reason (OIS) you mention.

[@Heffen89]

My colleages from the electronics workshop always slap me when I design in such bridges. AOI is also not happy with that.

[@jakehop-]

Drink each time Dave says "soldermask expansion".

[@fontende]

Mostly because of cheap manufacturer, in Japan they selling quite compact x-ray macro scanner for conveyor line with very high resolution, it's expensive and advertised against this also for very precise quality control of assembled batteries internals.

[@mawoodmain]

I think you need to read the jlcpcb capabilities a bit closer, they say if you want to guarantee that miss-registration does not affect your exposed copper you need 50um expansion. I've had hundreds of boards from jlcpcb and never had any more by even close to that much. Also these kinds of places automatically correct you data and practically never reject it. They are cheap due to their scale not reduction of quality, their process is much more automated then most Western houses...

[@EEVblog]

It says "The solder mask should have a minimum of a 0.05 mm "growth/mask opening" around the pad to allow for any mis-registration." Thats sounds like a *requirement* to me. Ok, so they might not enforce it, but the point is that boards can be rejected for this and it's something to watch out for. There are thousands of different manufacturers and they all have different ways of doing things. And for the pad-pad it says "To have solder mask bridge, the spacing between copper pads edge must be 0.2mm (8mils) or more." Again, that sounds very much like a requirement and not recommendation.

[@mawoodmain]

@@EEVblog true, I have had boards with intentional negative expansions (for hand soldered write connections) and zero expansion and not had an issue yet. They do auto cull thin mask lines between fine pitch components btw.

[@unh0lyav3ng3r8]

looked deliberate, but it was great to understand the reason why.

[@Andrew-dp5kf]

The problem with putting a deliberate short is it’s a real pain for PCB inspection QA steps.

[@dorusan]

9:08 don't walk around the house during the night with those eyes

[@UberAlphaSirus]

Looks like Data.

[@obiwanjacobi]

In this case it doesn't seem necessary. Plenty of room to lay a normal trace at the end of the pads. I would only do this when there is no other choice because of how wrong it looks.

[@bradpalmer2914]

SMD Assemblers absolutely HATE it when designers bridge pins. The subbie I used to work for would double the labour charge for any designs like this. So Designers don't be lazy, it will cost you more to assemble

[@ptamog]

I have been seeing Dave for years recommending solder mask between pads. In this video he adds that soldermask repels solder. Exposed FR4 also repels solder. I think that the only function is covering copper. Does anyone knows a source that proves me wrong? (Other than Dave please ;) Those thin soldermask fillets get detached and mess things. I try to avoid them.

[@EEVblog]

Googel "the purpose of solder mask"

[@paulbryson9921]

@@EEVblog I agree with ptamog. The primary purpose of soldermask is to prevent the solder from wicking down the attached trace. Funny how when the pads get closer together and solder bridges become more likely the solution is to remove the soldermask - and guess what ... the boards are still manufacturable. Just because others repeat a myth doesn't make it true.

[@pauldavis2108]

Soldermask was really invented for wave soldering anything other than single sided boards where you're entire board area gets exposed to liquid solder. Without a mask it's end up as a total mess with solder on all the traces and likely a lot of shorts. On the reflow process it still serves a purpose as it stops the solder wicking down the traces which would result in joints with too little solder.

[@Rx7man]

Louis Rossmann wanted to talk about that funky soldering job

[@mortezamodjtahedi3073]

what was more interesting for me about this #1353 was the software you used for pcb design. i tried to search your videos to see if you have any video about this, but i couldn't find(plz sorry me if there is any and i didn't saw that ) guess its nice to have a video about different pcb design app's and more important to say which one you use more and why ? i almost tried all i could found on internet but i forced to more use Altium designer because most pcb producers around me just accept .PCBDOC files …

[@jeff15]

Fantastic video like always. with out a microscope i can see why people would get confused. take care.

[@aravindhkuppusamy9893]

Dave's eyes 😊 green screen glitch

[@jimmy8653]

You spent 45 mins on talking about a jump pin lol

[@GlenwingThink]

Welcome to the channel new person :)

[@sanches2]

This brigde is a certain way to summon the AME (manuf. Engineer) to your desk to tell you this is not ok for optical inspection. Or in a smaller company the team lead doing the prototype soldering. For similar things i got a "friendly" slap on the neck from a very loud lady in the mfg dpt. When i was 24.( In this company we were all very close and i actually became an engineer there and she treated me like a little brother and i didn't mind because she had 20+ yrs of soldering boards:))

[@4shaw724]

I spotted a crossed over boged surface mount fuse Too! At 6.47 bottom right

[@skoopsro7656]

Dave, what is that word you keep saying. Kamasacha? Comegatchya? I get the context but I can't tell what your actually saying. Id like to see it written.

[@EEVblog]

Come-a-gutsa

[@skoopsro7656]

@@EEVblog thank you!

[@yousifalqallaf8095]

Thank you.

[@dmtd2388]

Luis Rossman just loves apple products so much that Apple hates him for spelling out reality of low quality apple designs

[@stephenwong9723]

You should power up the transponder!

[@GodLike-pe6kj]

The thing with all these capabilities is that they are really not "hard" limits. I´m pretty sure that some like JLCPCB will not check for solder mask expansion and all that stuff. For example, if you had no solder mask expansion, they (probably) would just manufacture it like that, if the layers are not aligned on the final board and some stuff no longer fits, thats my problem. The only thing that PCB-manufacturers really care about are things like hole to hole, min annular ring and stuff like that, where if they try to make a board which does not comply with these rules they can damage their drill bits or stuff like that. Again, I´m not saying that these rules are there for nothing, but in my experience (with cheaper PCB services) the limits are usually pretty soft, just don´t expect the board to be any good if you bend the rules.

[@kyoudaiken]

You wanna have traces with equal length if you got differential pairs, so it's not always possible to extend the trace length.

[@ghost-girls590]

In testting，I usually do this thing ，but for inspection that must be a big problem!

[@stephenbell9257]

It may be an intentional short but it is indicative of a lazy, sloppy PCB designer. Particularly in this case where it would have only taken the designer a few extra seconds to do it properly. In my early days of PCB design my boss quickly discouraged me by from using such short-cuts due to the problems it created in the factory assembly and QC of products. Sometimes a factory technician would expend considerable effort remove the apparent PCB short while trying to debug a PCB.