EEVblog

Only Dave can turn a simple question into a 1hr deep dive monologue into PCB layout and FPGA implementation.
FPGA power supplies, DC margins, dynamic power requirements, power budgets, high power designs, multi layer PCB design, placement, system considerations, power planes, copper weighting, stackups, routing, split planes, star grounding, blind and buried vias, high speed traces, return paths, EMC, and a whole lot more.
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[@testep02]

Damn, Dave. The wealth of knowledge you posses is unreal. I think of myself as a pretty good layout person, and I've done layouts for some ARM chips that I've been very proud of. But I have never thought about this kind of stuff. Of course, I've never worked with tolerances tighter than a frog's ass either. Your viewers are orders of magnitude better at not just PCB layout, but electronic design in general after watching this video! You, sir, are legend!!

[@liadsagi3]

We NEED more DEEP DIVES!

[@QuantumFluxable]

more deep daves

[@優さん-n7m]

The curve from some distance look great, but deep dive will just show a smelly cunt, not worth it.

[@steverobbins4872]

This video brings back memories for me. In the early 2000's I worked at a company that used massive bleeding-edge FPGAs in dozens of products. I was literally the only analog guy in a sea of digital and software engineers. One of my main jobs was to unscrew the bad layouts for dozens of point-of-load buck converters that made local supply rails for the FPGAs. Before I hired on the local Linear Tech FAE was constantly designing custom converter circuits for this company. (They kept him so busy that he practically lived there and he was SOOOO happy when they hired me.) But the LT guy just gave them the schematic for each converter, and didn't oversee the layouts, so it was pretty bad in terms of noise, step response, and EMI. (BTW, tweaking the compensation to get the best step-load response can make a big difference in terms of keeping a rail within the limits.) My other big tasks were: finding and fixing impedance discontinuities; reducing clock jitter and skew; and solving thermal problems.

[@goose300183]

Awesome! Having the role of "fixer" can be both intimidating and massively rewarding. Living life on the edge!

[@優さん-n7m]

Did you have to carry out power delivery netowork analysis?

[@steverobbins4872]

@@優さん-n7m Yes, quite often. In fact, you just made me remember something that might make an interesting video: source/load instability and the Middlebrook stability criterion. This company made several different card cages with big ac/dc power supplies providing power to the backplane, and a wide variety of blades with assorted dc/dc converters. You could have a hundred POL supplies running off the same rail. I made them include input filters on some of those blades with enough bulk capacitance and ESR to keep everything stable.

[@Graham_Wideman]

Can you imagine Dave doing the PCB layout on a big complicated board? He must lie awake at night with his eyes wide open for weeks!

[@davidgustafik7968]

Dave @ 35:23 "I can do a video on every single one of these properties" Ooooh yessss, please do :)

[@sablanex]

That's what I was thinking too lol :D

[@electronicstinkerer5429]

That would be amazing (and super useful)!

[@jorenjoly6488]

I'm hoping for it!

[@Audio_Simon]

This DC ground impedance stuff is exactly what makes good audio equipment design tricky. When you need greater than 100dB integrity on a 1v signal, yet have 10A dynamic current draws on the same circuit. Lower frequency than this FPGA stuff of course, and generally less complex.

[@EEVblog]

Yep, essentially he same problem.

[@testep02]

I wouldn't classify analog as less complex. You actually hit the nail on the head with your initial statement. Analog design and layout is some of the hardest design/layout work in the industry. It's incredibly hard to get right.

[@kilrahvp]

I'd really like to see PCB design files for a PC motherboard, these do need to supply up to 250A or so to a high end CPU...

[@byonnem7342]

where did you get that number from?.... Processors are on a 100W scale.. that means less than a volt supply?

[@kilrahvp]

Byonnem 130-150W is stock TDP, but you can go much higher when overclocking. My 5960X gets pushed to about 280W on full load.

[@quarzent]

@@byonnem7342 Its not unheard of for a high-end CPU to draw over 300 W at around 1.35 v when overclocking, so 250 A isn't out of the question.

[@IAmPattycakes]

There's also the xeons, I think the 8280 could peak over 700W, consistently over 500W at 1.3ish volts. That's at least 350A sustained. Absolute insanity imo.

[@tangerinq]

I think this is the most valuable video from Dave I've watched so far. A big thank you Dave for sharing your knowledge!

[@PplsChampion]

for a solid minute i thought you were doing some green screen effect around 4:30 your bg just looks like part of the board lol

[@alex_inside]

Electronics always just tears my brain up in a thousand prices. The only difference between this video and my professor ist that the this video makes me actually want to understand it all. 80% of the time a video on YT will teach you more than a 2 hour lesson. I love the enthusiasm.

[@jonka1]

@@Okurka. I would include TV programmes as well.

[@emmanueloluga9770]

@@Okurka. The less than .1% is more than enough to overcome that tho

[@xDevscom_EE]

We need to go deeper! Let's also talk about separating dirty digital power and sensitive analog power :)

[@EEVblog]

Got another hour?

[@xDevscom_EE]

@@EEVblog Yep, still hour before work :) Power separation is often important topic, especially today, when you have high-speed XVRs and normal core logic power. It's best to isolate (have a split in copper, connect only at source DC/DC) these (both "digital" powers) otherwise eye and xtalk on XVRs might not be nice. Lots of traps for young players (like EE designers that start to play with modern FPGAs).

[@Audio_Simon]

@@EEVblog Yep! And do people still use linear regulators for specific instances?

[@God-CDXX]

@@EEVblog yep

[@bitrot42]

Love the deep dive! Whacking a micro and some LEDs and connectors on a PCB is fun, but "real" PCB design with complex devices is a different animal. This gives me a much better appreciation of some issues I was only vaguely aware of.

[@youriklaassens7198]

I did not know that the Vdds are so narrow for different purposes in an FPGA. Thanks for the interesting video, Dave.

[@SteveMHN]

Please do more of these types of videos, they're great.

[@ngjinkai]

There are voltage regulators with differential remote voltage sense inputs - this solves the DC voltage drop issue. Also, pick a regulator with integrated driver FETs - less space required, better transient performance, less effort on layout and overall potentially less problems to be had.

[@simonoffenberger6129]

please more of these FPGA videos and deep dives

[@WXSTANG]

They also added the wires to move the high current rails away from the FPGA signal wires. Magnetic interference introducing signals into the signal wires.

[@FurkanBahadr]

I remembered why I hated FPGA and went for RF :D

[@modalen2]

A lot of traps for home-gamers in RF to...

[@FurkanBahadr]

@@modalen2 just simulate it....

[@modalen2]

@@FurkanBahadr haha

[@emmanueloluga9770]

@@modalen2 don't worry, I'm laughing in rf transients too

[@Gengh13]

Nice video, would love to see more of this style of videos on other topics of real pcb layout.

[@AlfredoMazzinghi]

Thank you for doing this video! It is extremely interesting and I really enjoyed it!

[@electronic7979]

Nice long video. i like watching

[@SeanBZA]

One guess as to why the wires are so long is that they were a standard wire part at IBM, used in some other assembly as a jumper wire or power connection to a pair of PCB parts, and were available off the shelf as a premade, precut and tinned part, just a little longer than needed, but well within the impedance limits for the application. Not the best, but used a current production part, and saved having another "custom for this application" part, instead replacing with a "IBM standard part number" unit, that would not require all the paperwork for having the custom part made, along with needing to have all the extra cost associated with lifetime buys. Just order IBM xxx-yyyy-zzz -a in production and it arrives ready made.

[@bashkillszombies]

I'm already Tracer.

[@atmel9077]

ATMega328 datasheet states "2.7 to 5.5V". Lol.

[@fedimakni1200]

This type of videos are what we really need :)

[@優さん-n7m]

It would be great to see you layout a DDR3 interface on multi layer PCB between an FPGA and a memory IC

[@DrakkarCalethiel]

The name of the commenter would translate to deathbringer. Probes The Monkey in the background makes me smile :D Great to see a followup, I also asked myself why they didn't run large power traces instead of the wires.

[@OmarMekkawy]

I think that they put the power supply at the corner because it could affect the high speed signals coming out from the FPGA ?

[@foreverAnkh]

I love these PCB design videos. They are extremely educational and hands on. Great vid Dave!

[@gorak9000]

Now, the next question is why is it Vcc when there are probably no (or very few) BJT devices in an FPGA, and millions of MOSFETS, so shouldn't the rail be called Vdd? Pedantic much? yes, when I'm bored... :-P

[@johnfrancisdoe1563]

gorak9000 The old CMOS logic data sheets did that, and it was extremely confusing for beginners. Plus it's usually emitters and sources connected to both rails, with collectors and drains facing the signals. So we all stick to the Vcc name from the early NPN + resistor designs of early diode-transistor logic. Those designs did slightly resemble the tube designs where it would have been the anode voltage rail.

[@gorak9000]

@@johnfrancisdoe1563edited to say: wow, i'm tired, you're right, of course the sources of both nmos and pmos are connected to the rails - being that the source and drain in FETs are essentially interchangeable, and the typical rail names of Vdd and Vss, I haven't actually thought about it that way in many years!

[@attel2091]

Ahh... the art of balancing trade offs that is called layout design. And add the sleek "industrial" mechanical design before preliminary electronics design or proof of concept... And hope that the customer doesn't use most of the features at once in hot countries or it will be toasty as there weren't any ballpark figures of the power consumption when everything was on and more than >30C ambient.

[@UpcycleElectronics]

Does anyone here have the Saturn PCB design tool working in a dedicated wine on debian? Care to share the settings that work? Please :-)

[@tzubin99]

Ooh, nice long video to watch on a rainy day

[@PilotPlater]

Great video Dave. Fantastic coverage of this.

[@sysghost]

Sooo *umh* .. I don't go in and calibrate all those voltages with my $20 Wallmart multimeter?

[@karlharvymarx2650]

I guess power conversion isn't done on the FPGA chip because of noise and/or heat? If so, why not a strap-on device with shielding and heat sinking and power? Seems strange to a mostly software guy who is still learning electronics that every time someone designs an FPGA circuit, they have to spend a fortune re-inventing the power supplies. I like programming my Cyclone V, but literally have nightmares about laying out a PCB for it.

[@LazerLord10]

Little quibble about power dissipation effects in the inner layers: The technical term would be *allowable* power dissipation. The temperature rise will be much grater for an inner layer, so they tend to be rated to carry less current to decrease the power dissipation and keep the temperature in check.

[@philipacovington]

Very interesting info about PCB layout! FPGAs are really great for those interesting in retro-computing or learning how a CPU works. I am implementing Ben Eater's 8-bit computer in an FPGA in a series of videos on my channel for anyone interested.

[@chuckpatten7855]

Many designers overlook the value of multi-ounce traces and when they do then they forget to actually build it into the board.

[@Pops180]

PCB design becomes 10x more difficult especially on a board like that when someone dictates connector position. Those wires were to not only keep the conduction losses (heat) off of the board but to maintain a clean ground plane for the high speed return paths

[@EEVblog]

Yes, I do go into the high speed return paths. PCB designers generally like having constraints like fixed connector positions, at least you have some rigid rules to route from. "Free for all" layouts lead to the inevitable half way through the layout "If I just move this connector over here..." which leads to perpetual insanity.

[@Pops180]

@@EEVblog sorry. Crying baby keeps me from catching everything. But to your point, you really want to keep sub circuits truly separate. Power connectors in close proximity to power circuits and IO connectors in close proximity to IO circuits. I think this board was comprised a bit by the artistic side of PCB design. It looks very symmetrical which forced the power supply circuits out of the way. Personally I would have jammed the high speed stuff to one side of the board and the power/low speed stuff to the other. But hey, all pcb designers are different and I wasnt there. Just my 2 cents

[@Krejstrup]

Q: Why are there a milion vias all over the place? Do they use multiple ground planes?? I don't get it :|

[@pdrg]

Also possible that the power in was originally coming in from top right, then the case designer decided they wanted a sleek line, or something? ie the board was sensibly laid out to begin with, then the spec changed to move the power connector!?

[@God-CDXX]

dam Dave even I can start to understand FPGA's with you explaining them

[@Nightowl_IT]

Hi, Dave the name translates to death (todes=>tot) giver (geber=>geben) and it is german.

[@billr3053]

I was hoping you'd say how thick the copper trace is, the cross-sectional area, and thus the AWG wire equivalent - for certain current limitations and resistance. That way you can show what those power wires would be - their equivalents, on a layer, if one wanted the same characteristics as braided wire. How wide would the trace be? Perhaps it may also involve heat dissipation problems if the layer is buried and radiation interference issues as opposed to wires "flopping around in the breeze".

[@Umovni]

EXTRAORDINARY... What other word to use (Serious brain melt...)

[@Bartyron]

You can make this stuff so comprehensible...

[@richardgoebel226]

Down the rabbit hole to meet the Mad Hatter! Curiouser and curiouser, Alice.

[@smerf1979]

it's sad actually that typical user has no awerness of complexity of modern electronics. Smartphones, WiFi's, huge TV's, etc. It's like casting pearls before swines.

[@EEVblog]

Very true!

[@urugulu1656]

can you make a Video on how to find the most important Information from a datasheet. because often enough i find myself just ignoring huge chunks of the datasheet thinking they Arent relevant here, the circuit Fails and after that some guy smarter or more expericenced than me Points me to a Point in the datasheet that i wouldnt ever have considered useful for anything. and thats why Things dont work i know this is an Ultrabroad Topic but Maybe General techniques and some Things to watch out for for different categories of popular chipclasses or circuits…? Maybe?

[@johnkubik8559]

You are looking at a 20+ years old design where I'm not convinced it has a VCC power layer. Today if you want big fat power planes just ask for it, not only it would provide power to your chips but it would avoid signal crosstalk.

[@VndNvwYvvSvv]

Cost and production time matters though. Nothing is free to "just ask for it".

[@aavv17]

Altium has a nice add-on called PDN analyzer to help out with this exact issue (DC drop, and current distribution in your conductors).

[@EEVblog]

Haven't tried that yet

[@PredatoryQQmber]

Damn, just wanted to watch first 5-10 minutes to get what's it about… Who knew that a talk about 2 short wires on a big old PCB could be so riveting ?

[@VndNvwYvvSvv]

I wouldn't exactly call it riveting, lol.

[@ctrlaltdel02]

Modern hi end GPU's consume hundreds of amps.

[@khronscave]

37:26 Anyone else screaming at Dave about that being "only" the INPUT to the buck regulator(s)? :P Granted, the distance between the regulators and the FPGA on the left is even more than that, but still...

[@khronscave]

37:33 Thank you :D

[@SuppleAloe64]

This is one of the best videos I’ve ever seen on the Internet, and I’ve been on it since the late ‘90s. Granted I have an EE degree now, so I guess that makes me pretty biased. :)

[@cypriendecosson]

The silk screen seems to show the wires in parallel to reduce the magnetic loop area. Maybe the wires were added to control the path and reduce magnetic flux leakage due to high switch currents into the smps and consequent coupling into high impedance inputs?

[@tedvanmatje]

This was very informative Dave and much like your older videos (which I miss...a bit) Thanks for uploading!

[@EDGARDOUX1701]

Very interesting Dave, for me was like 1/2 an hour! So informative. Thank you

[@todayonthebench]

Dave, I think you are generally waffling on a bit too much here. Voltage drop across the board doesn't matter for the core voltage of the chip. (for reasons stated bellow, but it is a long comment.) Nor do I think that the cables are there for any grounding related reasons. The power supply chip used in this monitor measures the differential voltage over the load of interest. So other ground currents adding voltage drops isn't going to effect the voltage over our chip. (unless one places the ground sense point away from the load of interest. Then its a different story.) And general practice with any high current (or high accuracy/resolution) supply is to put its sense lines at the load of interest, not at the output of the supply. Ie, voltage drop across the board is also taken into consideration. (Practically all CPUs, GPUs, and a fair few larger FPGAs also have sense pins (for both input and ground) on the chip itself, as to take away any voltage drops in the chip carrier.) This is though generally only the case for the core voltage of the chip. Not always for IO. (AC coupled signals, and RF tends to not care about a bit of ground lift.) The dynamic behavior of the supply can generally be accounted for with a fair bit of bypass capacitance. And yes, practically all transients can be dealt with by simple use of ample bypassing. (Though, this too is an area where one can fail. This is if one puts too much output capacitance at the supply itself, then it can overvolt the chip when the chip goes idle. Though, no bypassing at the output and the supply can radiate RF and ring like a bell....) But to end this whole comment, I don't even believe that the main DC in connector and the area for the wire to bond to is connected to anything else but the wires per say. My main reasons for why I think this is due to the screw hole, with exposed copper not bridging over to the ground lead of our connector. There is places for SMD capacitors, likely to cut down on EMI, but no connection to what I can see. Above the positive pad, we have a 10 Amp fuse, and what might be NTC resistor based inrush limiting before it jumps away with the wire. If something happens inside of the board is a different question. But a multimeter can likely answer that. So simply stated, I do not believe that these cables are put in place for any grounding related reasons. But rather just as an extension to get the power from the connector over to our board to board power distribution without interfering with our high speed signaling.

[@daverhodes382]

And you accuse Dave of waffling? Read your comment again, some of it makes literally no sense at all. And it's per se and below.

[@Sami.curiouslab]

is it also ok to put analog grounds above digital grounds?

[@gert_kruger]

Could be signal integrity issues. EMI coupling through the positive voltage rail to the ram chip. Routing further away decreases the coupling.

[@Graham_Wideman]

48:48 "ya moight have to call in the grey beard to operate yer reflow machine". Hahaha.

[@Roxor128]

What's this Imperial rubbish? You're Australian! We use metric!

[@mattjmwmatt]

I have a test on microprocessed systems tomorrow, does this count as studying?

[@inigoselwood9382]

Good luck!

[@r2daw158]

Great! Thank you for the video! Always interesting to learn about PCB (especially that complicated ones) power layout.

[@sanityd1]

More of this, by which I mean: do whatever you like.

[@dtiydr]

Very interesting and how to do the layers for an FPGA, cool!

[@byronwatkins2591]

Resistance is R=rho L/A. The area that a current must cross when entering or leaving a pin (given a complete power and ground plane) is A=2 pi r t; the circumference of a circle times the copper thickness. The thickness is dozens of microns everywhere and the radius becomes ~mm near the pin. This is a very small area for a single pin or via and this is why larger pads with multiple stitched vias are recommended for large current paths. So an area of 10^-8 or 10^-9 m^2 and a length of ~5 mm has L/A~10^5 or 10^6 pretty easily without substantial care and dozens or hundreds of milliOhm resistance. Additionally, 10 A flowing through the ground plane under the FPGA will cause a substantial voltage gradient across the chip. The wire's L/A = (0.02 m)/(pi (0.0005 m)^2) ~ 10^4 total, the large solder spot is a few mm, and this leaves no voltage gradient under the FPGA.

[@ScramblerUSA]

Sorry, haven't watched the entire video yet. Maybe Dave have covered it. Just in case want to point out that there is another caveat with using just a ground plane for high-current path. It's hard to explain without a picture, but try to imagine: DC-DC converter regulates its output, so we have a regulated voltage just between 2 points where voltage sensing occurs. If we were to use just a ground plane without black jumper wire, it would have caused a small voltage drop (more so it is variable drop, depending on how much current the entire system consumes at the moment). So path would look like this: "+ terminal -> line -> DC-DC -> groundplane (with undefined Vdrop) -> - terminal". Now, let's consider the leftmost FPGA. Its power path would be like this: "+ terminal -> line -> DC-DC -> FPGA -> groundplane -> - terminal". Here is the problem: current goes through the shortest path, so it will skip the {} part "... -> FPGA -> groundplane -> { DC-DC -> groundplane } -> - terminal" upon return. This will result in voltage increase over FPGA by the same unpredictable amount that is lost on the way to DC-DC converter in the ground plane. Nasty.

[@Mr.Leeroy]

19:04 How does die size translate to complexity of the chip? The odds are that it is simpler with a bigger die, at least because: a) it is probably not 7-10nm photolithography b) it is not that power dense IDK, maybe some FPGAs that break these points exist, but they are not generally draw hundreds of amps, require multi-phase rails and dissipate hundred of watts as modern CPUs do, even mid to high end desktop ones.. I'd be surprised if the most used fab scale for FPGAs is less than 28nm. 19:25 This is well know in CPU design specs and even consumer overclocking as Vdroop, is compensated on the fly in programmable power controllers and configured on UEFI level

[@Thermoelectric7]

One thing I didn't see you mention is the difference between voltage drop in the 16V supply vs FPGA supply rails... The voltage drop in those 16V supply traces would be of limited concern as it's irrelevant to the FPGA voltage input limits, those supplies making 2.5V aren't going to mind a 15V input instead of 16V. You're likely dropping more in the cable from the power brick to the input connector than in the PCB traces, if they went that way. As you say, ground plane separation will likely be the issue they're avoiding. The main thing they'd be worried about if they put those power traces in, would be power dissipation rather than voltage drop. When you get to those FPGA supply rails (being a lower voltage and likely a higher current), voltage drop would become much more relevant in the design, and as you say, those switching converters are likely "4 wire measurement" to compensate. (just my 2c, I'm only a lowly electrician)

[@IAmPattycakes]

Jeez, watching this video I'm glad I'm working with "simple" arm processors. Nothing nearly as nutty as those FPGAs with insanely tight tolerances.

[@JerryDodge]

Hey Dave, I have this big Dell monitor with a system board with obvious bad caps and a wire cluster which is fried (insulation crusty and falling off). I can find replacements for the board, but not for the wire cluster which is fried. 1) Do you think this monitor is worth investing in a new board? 2) What would you recommend to repair the fried wire cluster myself?

[@petersage5157]

20 thou is a "big, beefy trace"? I typically go for 80 thou for power traces on small signal op amps, coming from heavily stitched 180 thou busses.

[@guilgec]

As always great video, Dave! I really support more videos like that! And as an Altium fanboy I gotta say their PDN analyzer looks quite handy when handling all that stuff.

[@EEVblog]

Haven't tried that yet, I'm still running an old version

[@alexleblanc1187]

If you REALLY had to, you could cross the split ground plane with stitching capacitors connecting your two grounds (for AC return path).

[@qqqqqq6686]

I belive there was no place at all over all the layers due to FPGA signals going to the connector and RAMs. Desolder the jumper wires and check if there is connection on the pcb. If yes you can connect external let say 1 Amp current and measure voltage drop.

[@PeregrineBF]

If you have the space (not likely with an FPGA) would it help to run sense lines out as close to the load as possible from the switchmode supply? It wouldn't help the dynamic response much at all, but it could compensate for the static drop rather nicely.... And he covered this at 31:10 or so.

[@Antyelektronika]

In minute 35:27 you said about making videos about this properties, so would you do this? for audience :) Thank you for this video and more about this stuff would be grat :)

[@briancannard7335]

Wow, thank you so much for sharing! I wonder who and what for use these large FPGA boards nowadays...

[@ArieLash01]

Hi Dave the decoupling caps supply the fpga as it draws its current dc as the fpga is is a switching device I was under the impression that the bypass caps supply the current digital parts draw current in bursts with the clock .www.xilinx.com/support/documentation/application_notes/xapp623.pdf figure 1

[@allthegearnoidea6752]

Completely off topic. Your solar panels failed in a big way just thinking what would happen to the road ways. Hope your house was not damaged as I feared for your safety. Looking forward to your video Good luck best wishes to you and the family. Let me know if you want free tickets to the rail show in Sydney in November. regards Chris

[@ChaitanyaDhareshwar]

If they say deep web, they're talking about the eev blog. It's very, very deep... ;)

[@laernulienlaernulienlaernu8953]

There's IPC standards that set out the size of traces based on the current and whether they are on the surface layer or middle layers. It's another one of those things where there's pages of standards for something you take for granted

[@blantonator]

I think a big problem here is there are so many stitching VIAs, the designer has shredded the ground and power planes.

[@ambushb0y]

I wish you could do a deep dive on some of the boards I use at work....

[@hallohallo3412]

switching to imperial, killed the video for me haha

[@PankajKumar-zr3tv]

I have a question. Are electronics jobs going to die in future? can someone tell this?

[@MTBSelfieStickGuy]

Why is there A voltage drop on the ground plane? Around 29 min mark

[@laernulienlaernulienlaernu8953]

Could it be anything to do with the EM interference compliance tests?

[@2ftg]

Deep dive in to FPGA datasheets sounds educational, I'd watch that. I heard FPGA's are really choosy when it comes to VCC, they really need 1% or 0.1% resistors in regulator feedback to get the exact voltages. Because nominal voltages don't mean the FPGA is gona function exactly like the datasheet promises.

[@sablanex]

More deep dive plz

[@dawnminilla9299]

11:35 how do you decouple dc? Are you not still decoupling the ac component on the dc bus?

[@andysworkshopuk]

"FPGAs are weird enough as it is" ... you got that right! Great video Dave, one of your classics.

[@ElmerFuddGun]

The word is _mirrored._ - 2:22 ;-P

[@MaxKoschuh]

Todesgeber = (german) someone who "gives" death very interesting video though :-D

[@aliuzel4211]

Very good video. Thanks. I remember from early days APEX was just a glue logic in our project named SWAN (Storage over WAN, Gb Eth/ESCON/Fiber channel over STM-16) in 2000 at Nortel. There were huge 6 pcs of XILINX FPGAs, Fiber optic connectors, 77,76MHz PLL/2Khz / 1Hz clock networks, complicated JTAG chains, Freescale PowerQuicc as a host controller, laser .......

[@sergeantseven4240]

"You've got to build bypasses."

[@alexleblanc1187]

Given how FPGAs are very often used in low volume applications and have very specific power requirements (and have more complex fab), I'm a bit surprised that the standard way to use them isn't just FPGA modules (e.g. maybe large LGA modules with castellated pads for power) that just handle the complexities break out the IO.