I2C bus arbitration mechanism in Embedded C Animated tutorial

[@timmy610387]

It's really helpful. Thanks

[@EmbeddedC]

+陳昱廷 thanks for the feedback, keep following the channel

[@venkatnalla3632]

I happened to watch this video today and thought of offering these comments. Any master would indicate start of communication by pulling the data line (SDA) low when the clock (SCL) line is high. Not by pulling the clock low as stated at 2.07. The logic at every master (say master M1) would be, pull the SDA low when the SCL is high and keep it low until the SCL goes low and try to pull SDA high. If M1 is able to pull SDA high the M1 gets the bus. If it is not able to pull high means, other master is holding low it as the SDA is wired AND. So the M1 should back out now, giving the bus to other master and try again after STOP condition. The M1 would act as a slave until STOP condition and try to take the bus again after STOP. At any given time only ONE master will be controlling the bus while communication in progress, so the situation of both mater 1 & 2 writing the data to slave address 1111001, as stated between 5:17 to 8:12, DOES NOT arise .

[@mattakalyan1427]

what is actually the meaning of master disconnected from the bus? That Means any internal logic controller of the i2c mechanism will make the ic sop the i2c mechanism until the bus becomes high.

[@saravanakumarchinnasamy7947]

hi good explaination. Can you post the video on CAN Protocol?

[@EmbeddedC]

kzbin.info/www/bejne/gnK3aWl6bNKLqZo

[@yasirshahzad3732]

What happens when both masters attempt to access the bus simultaneously? Will they not disturb the communication line and cause synchronization issues?

[@re_pu_bli_c]

If two masters are working at different speed modes ( m1@ standard mode, m2@ fast mode), which master will take control of bus first?

[@vinodahuja1739]

Hi thank you so much for video. I have one doubt in wired AND. In above video you have explained a situation where both master want to write to slave but master 1 want to write 0 and master 2 want to write 1 since it is wired AND logic therefore master 1 win and master 2 will go to wait. But what if both master want to write 0. Wired AND of both is 0 . In the above video 7:55 I have doubt.

[@erbkgupta8679]

thanks

[@vinayprasad4748]

How come master know the slave address? We know it by data sheet but master how it come to know the slave address?

[@kavindranlycan8229]

Hi guys great job I just love your videos. Can you post a video on can protocol and it's respective programming tutorial

[@EmbeddedC]

+Kavindran lycan thanks for your feedback We will update soon

[@karthikeyansubramani5346]

If both master send below data at same time. master1 send 110 master2 send 101 Which master will take control over the bus?

[@desxcsw]

Karthik Subramani master2

[@rabbit92x]

why?

[@astghikavagyan1119]

@@rabbit92x it is wired-and, 1 AND 0 gives 0. That's why master 2 :)

[@venkateshravuri6011]

Clock synchronization means

[@pavann5883]

Can u explain with the embedded c code

[@rockjack2750]

What will hapend data of master 2 when master 1 complate its transmission and stop bit generated.

[@rockjack2750]

And also wired and meaning put physical and gate on sda line?

[@ZidZafar]

Where is the animation???😅

[@vscmTube]

he keeps mixing up the signals between SDA and SCL lines.... !!!

[@fariaanzum5913]

can you say a bit louder.your voice is inaudible.