Experimenting with static RAM

[@your-dad]

I love how he is learning with us!

[@dldnh]

Your experimentation process is a really great example, very helpful to me, to see where I have had questions, and you're answering them.

[@chrismarquardt]

Problem solving 101 and a good message: You learn best by making mistakes and fixing them. Thanks, enjoyed it.

[@Giepie]

That is why I like your channel - learning with your viewers 😁

[@GlennHamblin]

Thanks for sharing.

[@davidgari3240]

A testament to the robustness of chips from that (my) era. My advice is to get out of the design phase (drawing a schematic) before even TOUCHING the parts. How many programmers does it take to change a light bulb? Zero (0); it's a hardware problem.

[@jamesross3939]

Cool! That's the way to learn. I'm impressed you have that SRAM chip from way back! I need locate one or more of those. I have some modern large ones 512k x 8 .... i still aim to play with.

[@roberts7531]

One point to consider is that when switching from read to write for a short time the sram and the bus transciever are both outputting data on the bus, I think a better way would be to use the Chip enable line to disable the chip, then switch Write to read, and maybe the bus transciever enable pin can even be connected directly to the R/W pin on the sram. Also, when you start experimenting with the CPU, I recommend you to take a look at the 74LS138, I think you should have it in your kit, that chip really simplifies memory address decoding

[@timquadrat70]

I really enjoy your videos - we're at the same level and it really helps following your thought process. It's exactly my pace. Also seeing you mistakes is very helpful. Thank you!

[@markday3145]

I'm wondering if you could have gotten away without the bus transceiver chip if you used weak (like 100K) pull-up AND pull-down resistors on the input DIP switch. That way, when the SRAM is in read (output) mode, it should be able to drive an output signal despite the pull-up/down from the inputs. But, since your inputs come from single pole switches that just make or break a connection, one of your pull-up or pull-down would have to be stronger (lower resistance) so that when the switch is closed, and current is flowing through both pull-up and pull-down resistors, you get a voltage that is close enough to ground or VCC for the SRAM to reliably detect the logic level.

[@d614gakadoug9]

Using pullups would work fine. The datasheet specifies the part to produce a maximum output voltage of 0.4 V while sinking 3.2 mA, so something like a 10k pullup to 5 V would be reasonable. 100k is probably about the upper limit given the somewhat high "leakage current" at the inputs. Pull-down is less flexible because the output HIGH source current capability is considerably lower magnitude (150 µA source vs. 3.2 mA sink).

[@hesk4u]

Really enjoyed this video. I learned something about computer architecture.

[@RealJustinWillock]

You’re making huge growth from the last time I checked in well done!!

[@GMCLabs]

I think when we did this in school, we programmed the addresses 1st. Then rewired it to LEDs to read out the values.

[@iblesbosuok]

I suggest you to use three pieces of _4-bit coded hexadecimal rotary switches,_ a 74HC125 chip, a toggle switch (for read-write select), a push button (for CE pulse) and ULN2803. Thank you

[@DavidLatham-productiondave]

When you switch to read mode on the SRAM and before you've disabled the transceiver, do you have a bus conflict? I think there is a way to switch both signals at the same time using something like a 74LS157 multiplexer.

[@evugar]

👏

[@VS-hw6of]

2. ✌😉