Extending riscv-dv to suit your specific needs.

Extending riscv-dv to suit your specific needs.
The OpenHW Group has been using the Chips Alliance “riscv-dv” pseudo-random instruction stream generator to verify its CORE-V family of RISC-V cores since 2020. Each core has specific features that may not be supported by a general-purpose tool.
Mike is a functional verification engineer and manager who has been involved in all aspects of the discipline: simulation, emulation, prototyping and formal verification. He is strong proponent of coverage driven processes in the pursuit of first-time-right silicon.