RISC-V Verification: New Techniques and Approaches for SoC Validation

RISC-V Verification: New Techniques and Approaches for SoC Validation
RISC-V processor cores are becoming more complex and varied. The author has worked with multiple RISC-V core providers to extend their verification environments to meet modern processor verification requirements. The presentation proposes a range of test “layers” that extend beyond standard random instruction generation to include system integrity verification. This is accomplished using synthesis techniques that enhance the coverage that may be achieved. This presentation will demonstrate a number of these verification capabilities, how they have improved RISC-V verification, and how they may be applied to verification environments in general.
Adnan is the founder and CTO of Breker and the inventor of its core technology. Noted as the father of Portable Stimulus, he has over 20 years of experience in functional verification automation, much of it spent working in this domain. Prior to Breker, he managed AMD’s System Logic Division, and also led their verification team to create the first test case generator providing 100% coverage for an x86-class microprocessor. In addition, Adnan spent several years at Cadence Design Systems and served as the subject matter expert in system-level verification, developing solutions for Texas Instruments, Siemens/Infineon, Motorola/Freescale, and General Motors. Adnan holds twelve patents in test case generation and synthesis. He received BS degrees in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.