Electronics tutorial - 3/3 Driving multiple transistors in series

[@psyikoty]

Excellent, please bring more interesting circuit. Now when eevblog is mostly some general electronic talk i really miss good circuit analysis. I know it wont get you a big audience but i think it's a niche that will definitely get you a steady group of fans 😊

[@p_mouse8676]

I agree. For me it's the main reason I don't watch Eevblog that much anymore. Even for subjects I'm already familiar with, it's always interesting to watch.

[@FesZElectronics]

Thank you for the kind words! I will try to keep things up.

[@TheGovindtrm]

Liked your video before watching it

[@gharbisalem1254]

Great content I'm learning so much from your videos keep the good work and thank you for sharing

[@philippeversailles2170]

Really great, the circuits but LTSPICE trick too. Thanks

[@q12x]

Foarte tare ! Excellent explained and presented !

[@p_mouse8676]

Great video. Maybe it's worth to mention that the creepage and clearance distances you're talking about are for mains vs secundairy voltage. They are much lower and forgiving between (two) different secundairy voltages.

[@FesZElectronics]

Of course, the main use case of large creepage and clearance is for safety regarding isolation. At the same time though, if the circuit is very low power or otherwise sensitive to leakage currents then the same rules need to be applied.

[@p_mouse8676]

@@FesZElectronics Correct. What I was trying to say, is that often I see people using the same creepage/clearance values for secundairy voltages. Which is a little overkill.

[@FesZElectronics]

You are right. I also see rules taken out of context and applied everywhere, because "its better this way"...

[@EhsanAlnazi]

Really, interesting video.

[@lucasexequielibanez1832]

i have a question! i´m working on a final proyect about loads dc, and after see all topics about MOSFETs i wonder which schematic configuration would you recommend for a load with a power = 136W ???. I´m using four IRLZ44N in paralalel to handle that power and a btj to handle the gate of each one making a reduction voltage.

[@LeoBercoff]

Great tutorials! I wonder which is the simulator program you use. Is it free? Is any free one that you recommend for this kind of simple circuit analysis? Thanks a lot!

[@FesZElectronics]

I use LTspice in all my videos. It's free but its also pretty good. I have quite an extensive series of tutorials on the subject

[@simonpetermungai1973]

Instead of using bjt transistors, is the series explanation same for MOSFETs?

[@peterkutak]

why is playlist in order 3-2-1 😢

[@alexlindgren858]

i think i have a little more complicated sircuit. input is 3700vac rms and IGBTs are rated for 1200v. i cant do that resistor devider, do you think that i can hook up every base of the transistors to a seperate controll sircuit?

[@david_6063]

Hello again Fesz. Thank-you for another interesting and challenging video! I’ll add a few comment to express my perspective. First circuit (Q7, Q8, and Q9). There is feedback from the output to the resistor divider. Therefore, we cannot fully saturate at the output of Q9 because as the load is pulled down, the feedback reduces the drive to the bases of (Q8 and Q9). On the other hand, when we apply 0.4V to Q7 in order to cut the transistors off, current flows through the load and into the resistor divider, which prevents the output from reaching VCC. Second circuit (Q24, Q25, and Q26). Without the feedback and the reduction of base drive, the output can be saturated and can also come up to VCC. How to explain the differences in power dissipation during the linear regions? In the first circuit, during the transition from on to off, the emitter voltages of the middle and top transistors are defined by the base voltages as those base voltages rise with decreasing current. Because these base voltages come from a single resistor divider, which is driven by the load voltage they are in the desired proportion and the power dissipation in the 3 transistors is relatively equal. For the same transition in the second circuit, the collector voltage of the bottom transistor comes up first, followed by the collector voltages of the middle and top transistors. The power dissipation is therefore larger in the bottom transistor, less in the middle transistor, and much less again in the top transistor. How this is explained by the use of separate voltage dividers driven from the supply is not clear to me.

[@FesZElectronics]

Hello David, I guess the key to understanding the behavior and the differences of the 2 circuits relies on understanding the base voltages ratio to the upmost collector voltage. This is important since the emitter of each transistor is roughly at ~0.6V below base voltage, but more importantly, this is the same voltage as the collector of the next transistor below; for the sake of simplifying lets just say the base voltage is the same as the emitter. So in the case of circuit 1 the bases are supplied from a voltage divider that keeps the base at 1/3 and 2/3 of the upper Vc (collector voltage) - this ensures that the voltage drop Vce on each transistor is 1/3 of the upper Vc - so uniform power distribuition In case 2, the bases are supplied from fixed values - Vsupply (which is not the same as upper Vc) divided by 1/3 and 2/3; The 2 upper transistors are working in common base mode. As upper collector voltage drops, the first transistor to take this up is the up most transistor; once the voltage drops below VCC*2/3 then the upper transistor stays saturated and the next transistor starts to have a dropping Vce and so on. Its also important to add that since the bases are supplied from resistors, the voltages are not fixed, but rather can vary when needed. I hope this helps with the better understanding.

[@david_6063]

@@FesZElectronics Hello Fesz, Yes, that all makes good sense! Thank you so much for your careful and detailed response and for your time! You are the best.

[@alifeleparanj3688]

as always Very Nice!

[@t1d100]

Ooo, sooo good! Thank you!

[@andrzejpl9897]

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