FIFO Buffer - UART from Scratch - Part 4

[@weirdboyjim]

I have duplicate read2 and write2 net labels where there should have been read3 and write3. Thanks everyone who pointed it out. This would have been vary obvious when it came to layout the board.

[@twobob]

I absolutely love you doing them at the same time. Best ever. And Curse youtube for removing autoplay, makes adding comments at the end a right pain. lol.

[@weirdboyjim]

The breadboard and schematic? It can be a pain to sync up, but sometimes it's useful to get the schematic down while it's fresh in my mind.

[@jerril42]

I like this format . It offers nice continuity between concept and schematic. Interesting video. I've got to get some of those headers your buttons are in. Thanks James, take care.

[@weirdboyjim]

Thanks Jerril! Those are turned pin sockets, same strips I use for sticking modules on the cpu backplane. Before I worked that out all the switches kept popping out of the breadboard!

[@Otakutaru]

I am using your technique of designing the schematic using labels for college. Fair to say, they don't like it. But I do, and my wiring is always on point since I started binge watching your videos.

[@weirdboyjim]

Oh no! College is definitely a time to do what the teachers are pushing for. I'm very much self taught at that end of things and a probably have an impressive array of bad habits.

[@Otakutaru]

@@weirdboyjim Don't worry I'm not going to name or expose you, it's just that spaguetti wires are a nightmare to read

[@brandonmack111]

Very nice! This reminds me a lot of the double ended queue I designed as my first really useful circuit. It was pretty different, since it had a different use case, and it's really cool to see how you're implementing it for your CPU build.

[@weirdboyjim]

A double ended queue in hardware? Nice! I'll have to think about how I would do that.

[@brandonmack111]

@@weirdboyjim I used counter chips for my pointers, but ones that also could decrement. If you were pulling from either end, it would toggle the dec line. It was a pretty fun project, and a little more complex than I had originally thought, but in the end I had a really cool, functional DEQUE module :)

[@weirdboyjim]

Yeah, it's not a massive addition, I already have unused decrements, you just need a two sets of 4 line 2:1's to select which pointer is the read/write address.

[@dbarrie]

You've duplicated the read2 and write2 labels in the schematic! I'm sure you'd catch it once you went to lay out the board, but I figured a heads-up wouldn't hurt. Really enjoying the build so far!

[@weirdboyjim]

You are right thanks, It would indeed have been obvious during layout. Weird to be reminded so many people are watch this stuff close enough to catch mistakes like this.

[@cedAuz]

Hi James. Great video as always. To answer your question : great idea to show the schematic while you build. Interresting idea to build yout fifo yourself instead of going the easy way with a fife chip. Looking forward to the pcb with the tsop format.

[@weirdboyjim]

Thanks Ced! My plan for the pcb is to use TSSOP for the latch chips (8 of them, so it saves some space) but I'll do the control circuit with my usual SOIC.

[@Mark-px3rq]

I was immediately thinking of counter chips and decoders for the enable lines too. An alternative could be a couple of shift registers? Just shifting a bit round in a loop to indicate the read and write pointer - although exactly how you might initialise the circuit with a single bit might be complicated. You could compare the bit position with some XORs to know when they matched indicating the queue is empty. I don’t think you need to know how many items are in the buffer. Great series by the way. I feel inspired to build something. But you make it look so easy, and I know it won’t be!

[@weirdboyjim]

I'm not sure about your shift register idea, maybe try building it? I did have a very different idea with a series of latches where the value ripples forward.

[@Serotonindude]

hey james! 😊 the format of developing the breadboard and the pcb design in parallel is actually really good! it removes the boredom (to be honest) which comes up sometimes when there are 40 minutes of just designing the pcb in a row... i think it's a good mix! 🥳

[@weirdboyjim]

Glad to have the feedback. I've been trying to cut the pcb design down as much as I can without loosing it. I want this video series to be a full build record but I'm trying to mix things around as much as I can.

[@Serotonindude]

@@weirdboyjim yeah, i know. and watching pcb design is interesting in itself, for sure. but if u have seen it 30 times before... you know 😂 so i think the parallel format really helps with this issue... it also bridges the gap that was there before, between designing the pcb and what is actually designed, as those videos might have been seperated by several months

[@Rouverius]

Thanks for directing me to this. This is seems generally like what I was thinking for the Video Write FIFO. As you said, it would need to be a lot bigger to handle the size queue you're expecting. Seriously, kudos and much thanks on the crash course on EE and CPU design.

[@weirdboyjim]

If you look later in the UART series I make an 8-byte pcb version which is what I'm using on the UART in the vga videos. Definitely recommend looking at something more compact if you want it much bigger though.

[@Otakutaru]

Same stuff, but using an integrated memory chip instead of a decoder driving enables of individual registers

[@dennisdecoene]

And again top notch stuff!! 👌👌👌

[@weirdboyjim]

Thanks Dennis, your support is always appreciated!

[@tinygriffy]

Seeing the schematic every now and then makes it easier to understand whats going on on the breadboard, so its a nice touch, i like it ! And I was wondering if a couple 8 (6,4,whatever) pin strip headers, an old floppy cable and some heatshrink would make a good multi line cable for the breadboard ? And James, your voice is so soothing, I clicked the video and went to suspend at 7 minutes. Please consider making a reading book channel ! :see_no_evil:

[@weirdboyjim]

Thanks for the feedback. If I understand your suggestion correctly that's basicly what I'm doing with the dupont wires for connection's between breadboards. I've tested a few circuits out that way but the problem is they get very unwieldy unless you make a custom one of the correct length.

[@tinygriffy]

​@@weirdboyjim Yes, i thought single row 8-pin Dupont® wires would make for _easier_ latch connections. ... details ^^ I get the unwieldy thing though. Thanks for the reply !

[@JonnyBergdahl]

Interesting. I remember when UART chips with buffers first came out and we could use higher speeds on our PC's. Seems all PC IRQ's interrupted the CPU enough to loose characters. Plan to add interrupts to your CPU project?

[@weirdboyjim]

I'm glad someone else remembers the pain of relying on interrupts. Without a buffer no interrupt handler (or combination of them) could take longer than one character or you risk loosing data. Classic interrupts are not planned for this build, that's a scope choice to allow me to finish the build in a reasonable time. At this point I'd have to rework a bunch of parts that are already pcb's to retrofit them.

[@AjinkyaMahajan]

Nice build. A simplified vision will be to use universal register IC LS74198 with master clear input. It would save a lot of PCB space. Thanks ✨✨

[@AmauryJacquot]

the '198 appear to be made of unobtainium also, wikipedia states it's a "8-bit bidirectional universal shift register", doesn't seem that would be the right thing for the job

[@weirdboyjim]

I don't know that part (maybe a typo?) but there are lots of more complicated chips that would simplify the task. There are single chip fifo's around, there are single chip UART's with fifo's built in and of course you can get micro controllers with multiple UARTS. This is about the challenge of building things from scratch more than simply the end product.

[@AmauryJacquot]

at 11:00 there are 2 "write2" lines and the 2 "read2" lines

[@weirdboyjim]

This is why I make videos, other people check my work for me. Thanks for pointing it out, I hadn't spotted it but that's the kind of error that is very obvious once you start routing the pcb.

[@guntherschadow9383]

You should be able to use a pair of 74LS670 or '170 4 x 4-bit x register files for this.

[@weirdboyjim]

You could indeed, although I wanted to do it from first principles as much as was reasonable. In this you would have replaced 6 chips with 2 but it also would have taken away the easy expansion to 8 whole bytes I use in the pcb version!

[@simona625]

Hi. What software are you using for the wiring diagram please ?

[@weirdboyjim]

That is "EasyEDA" it's online, if you look at my profile you can see many of the schematics I've shown in videos. easyeda.com/weirdboyjim

[@m1geo]

@@weirdboyjim I can't see the FIFOs in oshwlab pages. Have you shared this?

[@richardlighthouse5328]

How about adding spi and i2c to the computer? I bet spi is easier because it is just a 2 opposite shift registers (Parallel In, Serial Out and Parallel Out, Serial In). I2C is just a half duplex synchronous uart.

[@weirdboyjim]

If you asked me a couple of months ago I would have said no, but I've actually been considering spi as a way of getting some storage (SD cards) into the build. Not 100% sure yet though.

[@bradywb98]

I hope you decided for instead of against 😉 I’d like to use raw SD for storage in my build.

[@lawrencemanning]

Amazing as always! Couple of points. I'm sure you wouldn't need a FIFO if you had interrupts. Just saying. :). I know that they'd be a pig because of the pipeline. It would have been interesting to try stacking the latch ICs. You only need access to two out of the 20 pins on each part, the rest could be tied together. Stacking them by soldering them together is a horrid but useful trick. The schematic resembles a netlist. They are easier to comprehend if you'd used buses and wires and not just labels. Likewise the symbols are all just representations of the physical ICs. Anyway fab stuff and top marks for persevering with those breadboard busses!

[@weirdboyjim]

You would be surprised, the majority of early uart chips had some buffering as the overhead of triggering a receive interrupt for every byte was nasty. Transmitting is a big deal as well, my current code spends large amounts of time looping while the current byte sends. Imagine the code for moving the cursor, it outputs a few characters (waiting each time) then performs an itoa8, outputs that string (With all the waits) and then repeats all that again. Just a few bytes if buffer will let it get on with those divides when it would otherwise have been waiting.

[@lawrencemanning]

@@weirdboyjim with a tx interrupt the interrupt would run when the holding register is empty, at which point it would populate it from memory. The processor can be doing other stuff. Am only going by the 6850 which IIRC has no buffering, except for the bytes in flight in both directions. Anyway the circuit is interesting and I'm interested to see how you get on with TSSOPs. One annoyance with those is you can't run traces between the pins, which is a pain when you are teselating them.

[@weirdboyjim]

Yeah, the 6850 didn't have proper buffering. The problem you get there is if the main code holds the 'i' flag to long, or any other interrupt handler goes on too long you loose characters. With a transmit interrupt you are basically guaranteed to be running at a reduced transmit rate due to the time it takes you to respond.

[@shashwathsundar]

Was wondering if u could've actually used those 16x4 RAM chips for this....🤔🤔

[@weirdboyjim]

Obviously you could, but it might not be as easy as you think. The main difference is that the IN and the OUT are completely independent. You can enqueue and dequeue alternatively, at the same time or any combination. This is necessary as you have no idea of the state of the send/receive circuitry in relation to the cpu. You would need a much more complicated circuit to mediate the read/write, probably not worth it for so few bytes but with a bigger ram chip it would scale much better.

[@weirdboyjim]

@oH well,lord! That would work, but yes they are very expensive. Of course this buffer circuit IS a duel port ram, with separate read and write ports.

[@djc1402]

Another great video. Are you going to have 'read ready' and 'write ready' signals to tell your CPU when it can read from and write to it? I cheated and used a UM245R for my UART and it has those signals, so missing or loosing data is eliminated. There is also a 4 bit x 16 FIFO chip 74hct40105 in DIP and SOIC that Digi-key is selling. I'm not sure if would be suitable in your case as it works differently to your FIFO, it is more like a pipeline than a circular queue.

[@weirdboyjim]

Thanks David! I haven't decided what I'll expose back to the cpu yet. I could just feedback the number of bytes in the buffer. Those fifo chips are pretty cool, two of those pretty much IS the module I'm designing but it won't have any led's or the knowledge that you built it from scratch ;-)

[@darer13]

if i understand, the '4015 is sort of a ripple buffer, that is, you would need to write to it 16 times to get the first data written to it? That does not seem helpful for the performance of this UART design. The '670 seems much more appropriate.

[@curtperry4134]

@@darer13 I'm using the 40105's in my build. Any data you shift in ripples all the way to the output immediately, so you can use as a regular FIFO buffer, you don't have to write 16 times.

[@TomStorey96]

These schematic symbols really are my pet peeve. 😣 If you used symbols with the inputs on the left and outputs on the right your schematics would flow a lot better, instead of being a collection of "chips with labels on every pin", which to me makes the circuit much harder to understand since you have to find every instance of a label and mentally reconstruct how it is all connected. But this is still very cool stuff. 😄

[@weirdboyjim]

Very few of symbols are setup like that on easyeda and it would add even more time if I was to sit down and create them all.

[@TomStorey96]

@@weirdboyjim I reckon you probably said that last time I moaned about them lol

[@m1geo]

I completely agree. They're a schematic diagram. They should show what the function is, not what the IC pinout is!