Finite State Machine Explained | Mealy Machine and Moore Machine | What is State Diagram ?

[@ALLABOUTELECTRONICS]

For more information, check this playlist on Sequential Circuits: kzbin.info/aero/PLwjK_iyK4LLCCpnnybEztvRqxpMyfgarS

[@vrakitine]

When I was earning my master's degree, I heard a lot about finite state machines (FSMs), but it was all theory - like clouds in the sky: there's a lot of water, but you can't drink it. I toiled for three months after graduating until I implemented my first FSM in code in 1981. Now, there is a programming methodology based on this concept - v-agent oriented programming (VAOP) - with many examples of its implementation. It's best to start learning about VAOP with this article on Medium: "Bagels and Muffins of Programming or How Easy It Is to Convert a Bagel into a Black Hole". With VAOP, you can implement FSM in any programming language.

[@bharathk8320]

As usual my guru excelled in this lecture

[@poojashah6183]

You are the best teacher, great explanation 👌🏻👌🏻

[@opengl-ve1bv]

i have exam tommorrow you saved my life thx!

[@ALLABOUTELECTRONICS]

All the best !!

[@opengl-ve1bv]

@@ALLABOUTELECTRONICS but what about the moore table? isn't right that the output will be like this 11001100 ? cuz it doesn't depend on the input? or it's just a transition table so it's correct?

[@ALLABOUTELECTRONICS]

@@opengl-ve1bv In case of the Moore machine, depending on the input, state of the machine changes and the output is the function of that present state.

[@gopikrishnanm5310]

As usual great content sir❤. I love ur way of teaching and it’s easy to grasp the content in one go. How many lectures are pending sir, am referring ur videos for preparation.

[@ALLABOUTELECTRONICS]

I think 5-6 videos more at the most.

[@amineadelbekdouche4596]

hi, thank you so much for the brief and concise explanation of the finite state machine. May i know what software you use for your presentation which i really appreciated.

[@KAA-cf3kj]

Sir, I think the state table for Moore machine is wrong... Bcoz the output only depends on present state so the output will be 11001100

[@SaurabhThakare-db9iw]

@@KAA-cf3kj I think so

[@muskanustad3834]

You are right

[@klaus9687]

@@muskanustad3834 you are wrong.

[@mayurshah9131]

Please continue such finest vedios

[@shaikshahidafrid8506]

What skills are needed for ece students.. And how to prepare for core placements.

[@rajbhushan3541]

strengthen your fundamental concepts of ece like dsd basic vsli, circuit analysis etc. Focus on any specific domain. like FPGA embedded etc.

[@galata1245]

Great video thanks bro

[@anirudhas-tn6ue]

11:19 Shouldn't the output be dependent on current state? In that table it is depending on the next state. Someone please explain

[@fodedoucara7073]

exactly! I was so confused as well

[@OviMG]

8:15, i didnt quite understand why on the mealy we have "2 numbers" on the transitions between states. Like we know that if the output for "00" is "1" it will "go" to "01" but what s about that aditional "0" from "1/0" ?

[@ALLABOUTELECTRONICS]

The second number represents the output of the machine for the corresponding input. In the mealy machine, the first number represents the input and the second number represents the output. I hope, it will clear your doubt.

[@samizaif4267]

somebody put his name on my Electric Engineering degree too

[@faneeshbansal]

Thanks for this video, please upload more videos soon on fsm sir

[@MohammadKhabiri-t6x]

thanks for this video

[@sathyagananaathaasattiamur4827]

14:30, What is meant by the input sampled right before the edge? I have also read this in a textbook but I have a bit of difficulty in understanding this concept.

[@ALLABOUTELECTRONICS]

Like I said, the input is synchronized to the inactive edge of the clock. So, before arriving the next clock edge, the output of the circuit will get settled. (Typically, the propagation delay of other logic gates will be less than half clock period. In this case, the input X is connected to the OR gate at the output, So once the input X is applied at the inactive edge, the stable output of the last OR gate will be available before the next active clock edge). Therefore, the best time to sample the output is just before the next clock edge. I hope, it will clear your doubt.

[@maciekcieslik8433]

What should we do if we have neither state table nor state diagram. To create the other one we need one of them. How can we create the first? Or maybe in exercise we have always one of them given?

[@ALLABOUTELECTRONICS]

Typically in the exercise, you will be given one of them. But like if you are designing the FSM by yourself from the scratch, then based on the desired outcome for the different inputs, you should first draw the state diagram or state table. And then based on that, you can design the FSM. In one of the video, through an example of the sequence detector, I have explained that procedure. Please check this video for more info: kzbin.info/www/bejne/hpPNn6eHm5imfcUsi=qWoOpjbaZ3sQCmAM

[@courcestudy933]

In other websites it is showing that In Moore machine the output depends on the present state but in your table it is showing that it depends on the next stage.

[@ALLABOUTELECTRONICS]

In Moore machine, output only depends on the present state, as it is evident from the state diagram. But in the second row of the table, by mistake, the output is written as 0. (when the present input is 01). It should be 1. For the rest of the cases, it only depends on the present state. But it does not depend on the next state. Probably, you might be meaning to say an input I guess. But by mistake, you have written next state. I hope it will clear your doubt.

[@courcestudy933]

yess thankyou but when present state is 10 then it should be 0 but it is written 1 , so i guess the outputs of 01 and 10 have been interchanged by mistake@@ALLABOUTELECTRONICS

[@muskanustad3834]

​@courcestudy933 you are right

[@GowthamsinghKshathriya]

Actually how the state diagram are writing without knowing state table or characteristic table Pls someone let me know 😢

[@chimachan6652]

Just a piece of advice: whether you learn English or try an artificial intelligence speaker except that ; everythng is great *thank you*

[@muhammedfazal697]

What's wrong with his English

[@klaus9687]

@@muhammedfazal697 hard to understand. had to see subtitles to know that he said falling edge.

[@fragux]

@@muhammedfazal697 He has a certain cadence that is quite repetitive and makes u not focus on what he is saying

[@EgeCalsma-uj5xt]

Amazing

[@sanjayshah9838]

V Good 🎉

[@mahamkharal3704]

• Finite State Machines: Analysis • Finite State Machines: State Table • Finite State Machines: State Diagram guyz i have presentation on these topic can anybody help me i have few questions like sequential circuit and FSM are same thing . moore and mealy is type of SC or FSM

[@kakrotchess]

pls change intro song

[@VIJAY-rq4ky]

😂😂

[@milanpramanik]

😂😂😂😂😂

[@TheRam359]

bro 😂

[@nihoni13]

No

[@erkebulanduishenaliev5506]

No music=no distraction=more concentration

[@Manishaa325]

Provide the notes on fsm

[@francescoliberi759]

are u indian?

[@ojasgupta1625]

@@francescoliberi759 yes

[@DorothyYoung-g6h]

Autumn Ridges

[@greencheese3717]

i don't understand the logic of the state diagram of the machines

[@ALLABOUTELECTRONICS]

The state diagram shows, how the state of the machine changes with the input. And in case of the Mealy machine, the output is also shown on arrow. While in case of the Moore machine (since the output is function of only present state), so output is represented in the state itself.

[@BoswellRod-d5g]

Gaylord Wall

[@sidharthgujjar7221]

hindi ni aati aapko ?

[@viettuto9605]

talk like google voice machine.

[@YaleFreda]

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