State Machines - coding in Verilog with testbench and implementation on an FPGA

[@venkatreddy5964]

I was really helpful, Even our professor wasn't much perfect, thank you sir and keep doing this kind videos it would be much helpful one again tank you sir 👌👌

[@TymexComputing]

13:45 - thats the question i was asking myself for 13 minutes :), so many state machines to consider :)

[@barsmertakpnar3136]

Very clear and understandable video thanks for informing us about fsm's

[@dansylee1]

I see that in the verilog code above, detect is a flopped version of (state == 2'b11); thus, the signal tap does show that detect is asserted 2 clk cycles after consecutive 0’s or 1’s of inbits.

[@GeorgeAlbercook]

Strictly speaking it seems like the second and third zeros are also a pair. This is a detects something but you don't know if it is pair or triplet.

[@matinfazel8240]

Thanks for sharing your useful knowledge!

[@InfiniteNesLives]

There is a problem where your state machine doesn’t detect the second pair when there’s 3+ matching sequential inputs.

[@shamilniftaliyev]

You are the king!

[@NostalgiaT]

im still confused how youre getting the 1s and 0s and which one they belong to

[@vaibhavbhasin1221]

ERROR ! great but some typo is there. 4:51 complete verilog for states, in state 1

[@i-manuel271]

This was a great video!!

[@valeriegirrens4715]

When I navigate to netlist viewer none of the options are available, what do I do to fix this?

[@athuldas44]

What is inbits that was shown in first program

[@harithabandara3212]

thank you!

[@TonyDaExpert]

Thank youuuuuuuuuu

[@NostalgiaT]

whats the difference between synchronous and asynchronous?

[@ngochuy7683]

thank you so muchh!!

[@deeps474]

thanks!

[@riddhisingh338]

Why wouldn’t you zoom in your test bench??

[@AkbarRajaei]

good job.

[@VarshithaAS-PSEC]

Please Explain the test bench in briefly

[@VisualElectric_]

Please check out my other channel for longer form/tutorial FPGA content kzbin.info/door/8gZeNz015waiQN5_-jvj7g