First project with Vivado

[@AHamAtHrt]

Got me started. Without this I wouldn't have known where to begin. Thank you!

[@mariacrocco1759]

This is a good resource for beginners. Very Clear. Useful information. Careful Clean Concise. Thanks and God job.

[@PatrickDelBarba]

These tutorials are probably some of the best on youtube. Thanks for making these available! These still work with vivado 2019 and the ARTY A7 board with some obvious changes to where you get the xdc files from

[@anch83]

Excellent tutorial and demonstration!

[@muhammadkashifkhattak7541]

very good tutorials, hope guys like you create more tutorials to spread knowledge..

[@mrunmoysamal3826]

Awesome tutorial! Just got my Basys 3 board today and fired up this program. 10/10 Thank you!

[@dheerajchumble5602]

Excellent tutorial sir. keep posting such videos.

[@nikithsaidheekonda7976]

Thank you so much. This tutorial is really helpful to get me through the ZED Board.

[@_Junkers]

I was looking for a tutorial of this nature. Thanks so much!

[@MammaArt]

Hello Tom, Could you please provide me the Code you wrote in this video. Thanks, Suman

[@engr.qaisarfarooq5336]

Very helpful, Great work Sir!

[@trandang0709]

I have followed your instruction and it's worked. Thank you so much. I hope you could create more instruction video like this to help us understand more about Zedboard and Vivado.

[@rithanathiths3613]

excellent tutorial for beginners

[@skelotar]

Thank you so much! Went through and was able to make my own IP and test successfully on the Pynq Z1

[@fabulous_peanut]

You're excellent at coming up with random words for acronyms lol, great vid though, thank you!

[@Tapajara]

At 16:06 you are suddenly editing the net to pin assignments. How did you get there?

[@breckyunits]

Very clear to follow. Thanks!

[@LL-ue3ek]

I do not have the board so I selected the same chip and tried to follow your demo as an exercise. I still did not successfully generate the bitstream after manually creating a constraint file; and I kept getting the same errors that you got in the video; the error was about the IOSTANDARD not being a specified value, even after I went into the "I/O ports" and selected specific values in the pull-down window. I think like you said it can get "absurd" in this issue. Why would Vivado make it so difficult and give users hard time like this.

[@mohammadhassan8127]

Thank you. Do you know how to find the design delay time?

[@lingesh4793]

Very useful , thank you very much.

[@laurenceearp7736]

RTL stands for Register-transfer-level, not run-time-logic...

[@marc-alexandreboechat5091]

while we are at it, I think PL stands for Programmable Logic ... too many initialisms. Great vid anyway, thanks!

[@HLSx]

I loved this tutorial. I think line 52 of Blinky.v should be : leds

[@marc-alexandreboechat5091]

Yes, you can actually see the bug in the demo at the end, leds[7] only lit going one direction. Off by one :)

[@Jocjabes]

A newbie question, how does that line, when implemented lead to leds turning ON? All I see is it being assigned. What understanding am I lacking here? Thanks.

[@fred123864]

Why is post synthesis simulation different to behavioural simulation for reset signal? In post synthesis reset takes more than one clock cycle to clear.

[@ucgiangnguyen8009]

do you have test_bench file ?

[@no5x937]

[Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. What are the remedies for these warnings?

[@darwincharters4293]

Great tutorial. Just one question - why didn't you have to create any timing constraints? If I try to follow your tutorial I get implementation warnings saying I should use "create_clock" constraint. Thanks

[@jaiminajmera0207]

To what is the clk speed reduced from 100MHz after divclk implementation?

[@no5x937]

[DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. Is there a Vivado setting, .xdc constraint parameter setting, or other remedy for this warning?

[@fteiyp]

Im struggling to get the zedboard to connect, how do you have the jumpers set up?

[@LL-ue3ek]

when you rotate light through the LED array, you used "

[@no5x937]

[Synth 8-7080] Parallel synthesis criteria is not met Am I missing some Vivado Setup setting that will remedy this warning? Or is this common and should ignore>

[@m.sharathreddy4356]

which vivado are u using in this video sir? Is vivado webpack supports that gui of constraints setting?

[@fabulous_peanut]

so you can change the voltages on a bank or it's already set? the zedboard_master_UCF says a specific voltage for each pin but in software there is more than one option.

[@kirkweedman5821]

You should not be using initialed regs in your clock divider. You also mixed blocking and non blocking statements in your sequential logic. These are not proper RTL design. You should have just run a reset signal into this block

[@rainermalzbender6329]

RTL does not mean run time logic; it's register-transfer level. Stupid old name, but now ubiquitous.

[@lrobie123]

must be a mechanical keyboard. lots of clacking noise. haha. gamers love those keyboards

[@saygnsisman927]

Your keyboard sounds like can.

[@jogeshsingh854]

😄

[@southfloridadventure]

Good teacher but need to get rid of that enoying keyboard sound