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Part 1 of how to work with both the processing system (PS), and the FPGA (PL) within a Xilinx ZYNQ series SoC.
Error: the "NANDgate" verilog file i wrote was supposed to be titled "ANDgate," but functionally was the same :p sorry for the goof
Link for Part 2: • ZYNQ for beginners: pr...
Thanks for watching!