FPGA Audio to my PC over Ethernet! PDM Microphone and CIC filter explained!

[@skate10110]

Great work! I love that people are now creating vids showing the build process for FPGAs

[@cesar_otoniel]

I was just looking for something like this. I just never came across it while looking for it but when I clicked in your channel from a coment. Thanks for sharing this!.

[@RobertMalahowski-eb2bk]

Fantastic! Thank you

[@cccmmm1234]

Wow, I was impressed how well CIC worked without a compensation filter. I have one or two of those boards. I should give it a try.

[@FPGAsforBeginners]

I was surprised when I tried it how well it worked.

[@FPGAsforBeginners]

Hi everyone! Resources in the description and also here! DSPrelated article on the CIC: www.dsprelated.com/showarticle/1337.php Source code for project and python recording script: github.com/HDLForBeginners/Examples/tree/main/eth_pdm_mic Timestamps in the description if you're looking for a specific part!

[@dymastro788]

Great video and channel! Subscribed

[@thegent5167]

Thanks a lot for this great series. I hope to see more videos from you soon because you are such a wonderful tutor and an amazing engineer.

[@cccmmm1234]

The easy way to think about this is that it is a moving average filter (which is equivalent to a FIR filter with all the weights set to the same value) followed by a down sampler. Let's think what happens if you have a moving average filter averaging 3 samples: The outputs are the average of samples: 1, 2, 3 2, 3, 4 3, 4, 5 4, 5, 6 ... Now if you follow that by down sampling by 3 then you would be throwing away 2 out of three results of the averaging filter. So: 1, 2, 3 Keep 2, 3, 4 Throw away 3, 4, 5 Throw away 4, 5, 6 Keep ... So if we look at the result (ie. just the stuff we keep) we get: 1, 2, 3 4, 5, 6 7, 8, 9 ... We can achieve that by adding up 3 samples, then outputting the result. This is exactly what a CIC does: it accumulates and dumps. This make it very cheap to implement in an FPGA.

[@drew-et1mm]

Very cool how i found the exact thing i was looking for

[@maswasembuze6488]

Nice!

[@AlexColeAldems]

Hi Stacey, these videos are really useful! I was wondering if you've ever worked with RF peripherals, and if so, if you may one day make a video or series on this? I work with software defined radios, but I am really interested in getting into the lower level details - something like the Analog Devices series of RFICs (AD9361/3/4 etc.). A long shot, but thought I'd ask. Great work though!

[@ggstats1345]

Great video!!

[@K4nj]

Thia Was pretty interesting to watch

[@stanleyyyyyyyyyyy]

Brilliant

[@absurdfatalism]

Excellent video Stacey! The neat "CIC is same as/can be configured to act as moving average" is something I wish I had more intuition about. I was with it up through "a whole bunch of counters offset by one" and how thats a moving average - but then getting into how that related to a specific desired frequency response and configuration of the CIC IP I need to think about more...

[@FPGAsforBeginners]

Thanks! Yeah the filter part can be a bit counter-intuitive. It was only recently that I thought about the fact that a moving average itself is a filter, which has its own frequency response. It makes sense that it's low-pass (the output is more 'smoothed' than the input, and that means the jaggedy-high-frequency-edges are taken away). And finite (only D samples in the past are considered). So in practice it's a pretty bad low-pass FIR. The multiple-stages part makes it less-bad (extra stages improves the noise floor a lot, at the expense of taking up more space). It happens to be a good option for this application because it's significantly fewer resources and slightly easier to configure than a full FIR. Maybe I'll implement a CIC in PipelineC at some point as my first PipelineC project :)

[@duality4y]

this book "The Scientist and Engineer's Guide to DSP" is such a nice read to learn about all that stuff. I recommend it.

[@wisnueepis3593]

Cool!

[@arzazimohammed]

great work i have a question i want to transfert video from fpga to another fpga i have done tranfert video from fpga to pc with petalinux in second step i need to do the reception with the second fpga and show the video by vga if you could help me

[@AggressiveMenace]

One question, and pardon me if it's a bit miscellaneous. Aside your hardware engineering background, are you a software developer/programmer/engineer?

[@hightlightlol2106]

Seems that your project is similar to mine. Im trying to send HF radio signal received by an antenna to PC thought Ethernet to draw the spectrum by FFT algorithm. I’m struggling at CIC filter to down sampling from 50mMHz to 200KHz. DSP on fpga such a whole new level which need to learn more to handle.

[@FPGAsforBeginners]

First off, apologies if you know all this. I don't mean to assume you don't, these things are just hard anyway even you do model it all. I have many memories of digging through my simulation sample by sample to find where it was different from the software model. Hope you don't mind the unsolicited advice :) The biggest recommendation I can make for DSP pipelines, especially big ones, is modelling them first in matlab/python, and checking the simulation results against what you see in software. Especially if you're coding a CIC yourself, having a software model can help you figure out where your FPGA is deviating from the actual algorithm. Second recommendation is to check your datatypes are long enough to have the amount of dynamic range you need. Usually I code a second version of my algorithm in python that models fixed point and checks what dynamic ranges I need. Third recommendation is to add in debug muxes in your pipeline to enable/disable different pipeline stages to check if they work individually. Kinda like how I started with ethernet, then added audio, and hopefully will be adding window/fft. Usually checking each stage individually helps a lot.

[@hightlightlol2106]

@@FPGAsforBeginners I know some basics of Python but never use it for DSP, can you recommend some courses or books to learn more about it?

[@cccmmm1234]

I think you will first need to mix the 50MHz with a local oscillator, then run it through a low pass filter. I don't see how you can really do just what you are doing with a CIC.

[@HalfLife2Beta]

Hey why input data width is 2 bits and output data width is 32 bits ? I thought PDM was 1-bit modulation (either low or high) ! Thanks in advance and very nice video

[@FPGAsforBeginners]

You're right, PDM is a single bit. Input data to the CIC is 2 bits because it is expecting a signed signal. I made the MSB zero so that it's always unsigned, and used the PDM input on the LSB. This works as long as I remove the DC offset at some point. The CIC has a gain of 30 because it has 5 stages and decimates by 64, and log2(64^5) = 30. Output size is input size (2) + gain (30) = 32.

[@HalfLife2Beta]

@@FPGAsforBeginners Thanks for ur reply. Could you also explain why u chose 5 decimation stage and D=64 ? 2.4 MHz/64 = 37.5 kHz, why not have chosen 48 kHz ? Or its not possible to decimate by fractional amounts so u chose a little bit less audio frequency?

[@FPGAsforBeginners]

@@HalfLife2Beta You can only decimate by powers of 2, so if I chose wanted 48k I could have used a frequency of 3.072M on the mic. I don't know if that's in range for the PDM microphone though. or decimate by 32 and use a clock of 1.536M. I actually can't remember why I chose 2.4M over 3.072M, it was in my calculations initially. 5 stages because it improves the SNR and reduces the noise floor. 1 or 2 stages the SNR would be lower.

[@HalfLife2Beta]

@@FPGAsforBeginners Thanks again for your answer. This kind of stuff I find actually hard to produce with the design choice and Verilog code in itself, it would take me probably one month to do the same so GG for making it & documenting it ! I would like a video covering FIR filters & CIC filters more in detail if its possible because its very interesting !

[@FPGAsforBeginners]

@@HalfLife2Beta You're welcome! This is one of the reasons why I started the channel. The learning curve is so steep with some of this stuff - my first DSP pipeline took me like 3 months to get right! - and resources can be hard to come by, so it can be slow going and frustrating for people who are learning them. I'm glad this helped you!

[@ktofa3822]

Hello, please if you can analog ic design courses.Thx