FPGA/SoC + DDR PCB Design Tips - Phil's Lab #59

[@th3magist3r]

Thank you for providing this content. Specially for free. I see in you the professional I want to be in a few years ! You are a legend !

[@PhilsLab]

Thank you so much, Alexandros!

[@jakobhalskov]

Awesome practical after having just watched all the great Rick Hartley videos and presentations available here on KZbin. I enjoy following your content, it is a great source of knowledge and inspiration for the electronics videos/projects that I am working on.

[@PhilsLab]

Thank you very much, Jakob - very glad to hear that! :)

[@spankymitch]

As an experienced FPGA design engineer, you really hit the nail on the head with this video. Every young engineer wanting to take the next step into FPGA layout design should watch this video. Bravo!

[@PhilsLab]

Thank you, Rio!

[@acalinp]

One can see you really know what you are doing, by the way you explain things. I feel you truly understand each concept you approach from top to bottom. Your channel is the only one I found doing that. Thank you for doing these kinds of videos, I wish you only success in life!

[@pradeeplanka6976]

Thanks, Sir, Lots of very valuable practical stuff for high-speed and dense PCB design in a very short video. Love to see more.

[@AlejandroGarcia-rk5lc]

What a great content to learn. Every time you post a video related to PCB Design I learn a lot by watching it and it gives me more confidence in pursuing my dream job, which is in fact PCB design. Thank you for giving all this for free and I'm actually waiting for an advanced course of PCB design to be launched! Finally, I encourage you to explain step by step a 4-Layer PCB design and with a separate ground for Analog and Digital (with a uC, not as complex as with and FPGA) if it not posted yet as it's very basic in a more profesional way and it has concepts such as stitching vias and stitching capacitors that are crucial to know

[@TonySingh7]

Can't wait for this course to be release, it will be epic!

[@dabdoube92]

Good quality teaching. Deserves the subscription to the paid course. Keep it up Phil 👍

[@PhilsLab]

Thank you very much!

[@JLCPCB]

Great video Phil!

[@johnstephenson4428]

Thanks for sharing looking forward to you class on how to design this board!

[@saitamapreetsingh3057]

You are great Sir ! May god bless you for sharing information and knowledge with us !

[@Theineluctable_SOME_CANT]

Wow, that's nice and technical and practical. Shall watch it later.

[@ahyungrocks5509]

As a hardware design engineer in the past, I was in charge of the schematic aspect. The PCB layout are typically done by a layout person (non engineer) who usually is exceptional in the layout skill. On critical circuits (ex. high speed, SAS, DDR5/6), engineer often provide guidance on how they want their boards to be routed.

[@piclife1178]

Very interesting video, thank you. I have used a number of PCB packages and my experience with Altium was that it is the most difficult to learn as it is filled with historic artefact functionality and unnecessary features giving it a real bloatware feel. I also found it to be the most buggy and one of the most expensive packages around. Sadly, aggressive marketing seems to have made Altium the go-to package for a lot of people but really there are better and far cheaper PCB development package out there and they all get the same job done.

[@heliumlabs]

Have loved KiCad more than anything

[@user-qf6yt3id3w]

These are great. I'm mostly a software guy and I've always been a bit wary of DDR/FPGA/High speed PCB design.

[@motion1776]

Great Video as always, How did you chose those connectors? Im asking because in most datasheets for these types of connectors there is only a "Support X GB/s" and not much more.

[@panda_santo]

Thank you so much sir for this tutorial 🙏.

[@PhilsLab]

Thank you for watching, Santosh!

[@MegaTraxxas]

Thanks for this valuable knowledge you are sharing with us

[@Leezorc]

Amazing content as always!

[@at0977]

Did you control the impedance on singled ended DDR4 traces such as address and data lines? Essentially, are the DDR4_ADDR and DDR4_DQ width different in inner layers compared to outer layers

[@garciabengui9173]

Thank you for this video. I have a question about DDR3 routing, in your layout the address, control and command signals are in different layers, can't this cause synchronization problems? The technical document recommends routing these signals in the same layer.

[@PhilsLab]

You'll have to keep track of Z-axis (via) delays if you route signal groups across different layers, but it's entirely possible.

[@garciabengui9173]

Thank you for your reply.

[@Zapho300]

I've never really felt hindered by Kicad before until I saw this video. You've certainly highlighted the benefit of Altium! Now if only I could justify the price...You mentioned that you avoided using microvias in this design. Do you mind me asking what size vias you used around the EMMC? I'm routing one with the same footprint at the moment and I'd also like to avoid microvias so I'll need to use the smallest via that could still be reasonably reliable.

[@animatrix1851]

Go with the smallest via that ur fab allows. I have a similar design with 0.42/0.2 vias, I think 0.35/0.2 was accepted too with my fab

[@sanjikaneki6226]

nice Why did you use 10 layers and not 12 or 8? what made you chose? About those board to board connectors why not use: gnd signal signal gnd signal signal gnd ? it would save some pins and also have all of them referenced , Or am i missing something?

[@RixtronixLAB]

Nice info, well done, thanks :)

[@bhupendersingh2604]

Where to find the delay time and skew for particular diff pair

[@nerosy2341]

Thank you, finally, i have been waiting for this video ! BTW do u prefer any signal integrity simulation tools we can use ? (free or not so expensive if there is any)

[@CallistoPili]

nice video, Are you also planning to make a video with similar design with KiCAD?

[@krnnjhee36]

Can you please tell how much time did you spend on this board ? Thank you for this excellent video.

[@PhilsLab]

Thanks! I spent about 2 weeks from start to finish, all the way from part selection to finished routing.

[@wthornton7346]

Brilliant run through Phil, many thanks. Apologies if I missed it but how many man hours in a work of art like this? Also, did the board work first time, or were edits needed after prototyping?!

[@mashurshalehin4972]

Hey Phil, please do something based on esp32 c3 if possible focusing on the wifi antenna design strategy. This will help me a ton and hopefully will help a lot of hobbyists too.

[@vladik8843]

? Esp32-c3 comes in a mini module with antenna for 2 bux... Why would u waste time to do anything else.

[@leifefrancisco7316]

Thank you !

[@poorchava]

Do you mind disclosing how much are the PCB and assembly gonna cost and who will do it?

[@PhilsLab]

I'm getting three made. I had the Zynq in stock (which cost me about 60 USD a piece), and then the PCB + assembly + remaining components cost me about 800-900 USD. So around 1000 USD for three which is very reasonable in my eyes, for fully-assembled, 10-layer PCBs.

[@mikael5743]

Thank you Philip

[@PhilsLab]

Thanks for watching, Mikåel :)

[@zoroxide]

Your content is very beautiful ❤️

[@PhilsLab]

Thank you :)

[@rjordans]

Great video again, thanks! Considering the importance of proper power integrity, do you plan on simulating some of that as well or is this a best effort kind of thing?

[@greggregory2267]

Hello - for propagation delay - exporting values from Vivado are for example in this format Min Trace Delay (ps) Max Trace Delay (ps) A10 RSVDGND 27.853 28.133 A3 GNDADC 31.635 31.953 A4 VCCADC 30.131 30.434 A6 VREFP 27.116 27.389 A7 DXP 20.476 20.682 A8 M0_0 25.429 25.684 Would really want to understand how to use above min/max from Vivado in Altium Thanks

[@theweekendful]

Nice video!! But I have one question, you mention that length tuing has to be done for almost all high speed circuits, but at which frequency is it condiered high speed and do we have to bother? Thanks!!!

[@myetis1990]

this is helloworld question in hispeed pcb design BW =0.35/Tr where Tr is rise time in nanoseconds BW is bandwidth in gigahertz bw over 100 mhz starts to be an issue in signal integrity aspect, so probably you should consider match the impedances and tune the length

[@parmmohan4603]

How do you determine how many layers you need? Do you add layers as you route or just have a standard setup.

[@piotrlenarczyk5803]

Thank you for video.

[@PhilsLab]

Thank you for watching, Piotr.

[@MdMubin-bp7wp]

expected to see the routing part in detail

[@kapishpotnuru1883]

Great video

[@PhilsLab]

Thanks, Kapish!

[@danielmusat597]

Why don't you use the transparency in the PCB view? It looks much clearer and one can see very easily where is a pad and where is a trace and where is a poly. It is a very useful tool that differentiates Altium from other design environments.

[@anjayv8347]

Phil why prefer to spread the power pins on to larger copper pours as the connection to the pin is thin? Any specific reason or a resource that would explain this?

[@cheese7221]

Even though the power pins are thin, we still want to minimise the overall resistance (reduce I2R losses) on the power net by immediately fanning out to the wider pours/planes and connecting to power planes (where a power plane can typically act as a more stable reference voltage). The manufacturer is simply limited by the package they use (depending on the current levels, many controller ICs will share current on multiple pins). In addition, wider power traces reduce parasitic inductance which can worsen performance of the switching converter.

[@nicoladellino8124]

Impressive 👏👏👏

[@PhilsLab]

Thank you, Nicola!

[@mth469]

The Schematics please, sir.

[@theonlyari]

I wish I could get altium to show my internal planes like that. Whatever altiums default way of displaying planes is really hard to look at

[@maximus6884]

I wish this was done using KiCAD. Can you advice if this is not possible to do using KiCAD?

[@PhilsLab]

You can definitely do this in KiCad. I find certain tools far more helpful in Altium to do this kind of design.

[@abddoabdo9613]

How to sign in for this caurse

[@funkysagancat3295]

I would love to take the course but unfortunately I don1t have enough money :(

[@enginstud8852]

I want to reach your level in electronic but it’s difficult to do it alone… I am very interested in your courses, I would take them if they were on udemy because of the price…

[@sc0or]

I wonder how you was so lucky, Sir to bought a power management IC? They completely forgot to order more. So, now it's still possible o purchase some SoC chips, but no PM IC available, so the processors remain useless.

[@PhilsLab]

Yeah, I purchased all of the main ICs before starting the design. Unfortunately, that's the way we'll have to do it for another year or two...

[@DehimVerveen]

@@PhilsLab Yea, this chip shortage we're in is really annoying. One moment a chip is really well stocked, then a little later, you'll have to wait a year or so before it's available again. I've just finished a 4 layer FPGA design. Just waiting for the PCBs. I hope I haven't made a terrible mistake haha! Looking forward to future videos on your PCB as well!

[@jasontoo]

madman loadout

[@tamaseduard5145]

👍🙏

[@hengzhou4566]

Can you give an FPGA/SoC + HBM PCB Design?