FPGA Timing Optimization: Optimization Strategies

[@adamfranklin3129]

I'm a former student of yours now doing FPGA development in industry. This has been a wonderful resource. Thanks!

[@andyhaas5366]

This is an amazing talk. Thank you for the incredibly clear explanations. They should teach you these things EARLY when introducing HDL. I'm only discovering it now after several years of sloppy and slow timing in my designs!

[@mbuaesenju8514]

Thank you, Dr. Stitt.

[@BorealScott]

Thanks a lot for sharing!

[@arunuday6109]

Excellent Talk

[@tombouie]

Thks &; Over my head but if I watch enough I will get there.

[@Асад-ЭрдоГад]

Strategy 1 is not a thing. It should make no difference with what constant value you compare. It just changes the logic function of the LUT at which partiicular combination of 'a' bits it outputs 1 and otherwise 0. Also worth mentioning is changing synthesis options that can sometimes allow optimize better for a particular design. I have a recent case that switching synthesis strategy, and a 1 check box in particular, improved timing by approx 1ns on the failing paths.

[@flyinginthedark6188]

But he explicitly said that the value is not constant and comes from a register. So it's not known at compile time. In that case it will help. To check this I wrote some small code examples and found that full equality of two 6 bit signal uses 2 LUT4 + 1 LUT6, but comparing to zero just uses 1 LUT6.