How to fix Timing Errors in your FPGA design during Place and Route, meeting clock constraints

Learn how to fix timing errors in your FPGA design. I show a Verilog example that fails to meet timing, then show how to pipeline the code to make it meet timing once again. Breaking up your logic into smaller operations will help lower propagation delay and get your design to run through the Place and Route part of the Synthesis tools correctly.
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[@ufester27]

Thanks for the video. It is always helpful to be able to glean insight from experience.

[@jaspritamsingh9178]

That is absolutely spot on. Perfect, short, crisp just like all your content. Thank you so much for all this content and keep this up, always looking forward to your content. All the best and thanks.

[@TheAnilmaddala]

Was worried because it's been 6 months since your last video. Good to see new video!

[@_pilly]

Thank you so much!!! Been looking for a video just like this one!

[@ewanwordsworth1592]

This is a fantastic video. Thanks so much for putting this up. Simple concept, but immediately helped me work on timing closure of my complex design, which I was struggling with.

[@rishabhsinha8140]

Brilliantly explained !! I regularly learning from your videos.. Thanks.

[@sumukhabharadwajmohanrao853]

Just brilliant! You explained it in a very simplistic manner and that's what really needed. Thank you so much. Hope you also explain adding different timing constraints to the SDC file. :-)

[@adamtheld]

Glad to see a new video! I’ve been playing around the go board, and it’s a great dev board for a hobbyist like me!

[@muniswamy100]

Bang on target. Great effort, practical demonstration. Truly appretiate it.

[@HalfLife2Beta]

Thanks for your video it really made me understand quickly the concept, much clearer than my course I followed during my studies!

[@shreshthadeshpande7043]

A good insight of Timing Analysis. Helpful!

[@wunan9879]

This problem really confused me for a long time! Very helpful video, thank you a lot !

[@briancooper2737]

I would have never thought that such a simple math problem would have caused that kind of trouble. The fix was easy and intuitive, when you think about it. I guess that is the thing though, you have to figure that out first. Thanks for the help. Nice to see some new content.

[@quackquackwalabattak4689]

Welcome back to KZbin !

[@efeberkayyitim2435]

Good to see you Russell

[@prolixescalation1932]

Just leaving a comment for extra oganic traffic under the video and to express gratitude. Thank you for this video, addressing the issue straightforward in beginner-friendly manner. Quality content!

[@ahmedamraniakdi2143]

this is the type of content i like, thanks

[@bilalhabib2001]

Excellent demo, love it.

[@WisseSpring]

I recently did my first ever FPGA project targeting Kintex 7 where I of course encountered timing errors. In my case it started failing when trying to do 34-bit division @ 100 MHz. After seeing this wonderful video, I'm very surprised that I almost got away with comparatively much more complex operation. Was not aware that there's such difference between FPGA hardware! Maybe it came down to something else? Just for reference: I later learned about how expensive division is and reworked my code using different approach in combination with fixed point math where you multiply with "fractions" to divide.

[@AbdAlhaleemBakkor]

Thanks a lot man , I learned a lot from you 🖤🖤

[@jl3586]

Thank you for another great video

[@mahmoudtantawi93]

Great video! Thanks very much

[@wi_zeus6798]

Thanks a lot for the videos!

[@pavanhegde1933]

First comment. Your explanations are easy to follow 👍👍

[@Alex-ri1zn]

Great video, thank you very much. By the way, do you usually use the "`default_nettype =none" directive in your verilog/systemverilog designs?

[@timonix2]

Very often you can do a much cruder version of pipelining. Just add a pipeline stage which does not do anything at all. The synthesis tool can see that the in-between data is not used and will move around the logic to get faster timing. No thinking required.

[@Calphool222]

Thanks so much for this video. I've got an FPGA design I've built and have been selling to friends (basically for cost), and I've struggled with timing stuff because I didn't really understand how to set up the constraints file, or how to fix timing errors. My design has 3 clock domains and video lines for input. I could get it working on the bench, but then when it was in the field I'd get weird reports of the video flaking out. Eventually through trial and error I basically *accidentally* fixed most of it with pipelining (though I didn't understand why that fixed it). Now I have a better theoretical understanding. Is the syntax for the constraints file the same for all synthesis/dev tools? I use Quartus on my Cyclone IV board (when I'm not working on the Go board of course), and I've gotten really confused on the syntax for the SDA file. I did discover that there were some "derive" commands that I didn't really understand, but they cleared up a number of timing errors. Anyway, thanks for your videos. They are much appreciated. For whatever reason this kind of training (basic context setting stuff) is very difficult to find elsewhere. Everything wants to throw you into the deep end of the pool before you even understand what swimming is.

[@messiweltmeista]

thank you very much, I'm in the middle of my bachelor tesis programming an FPGA. I haven't met the timing contraints too serious yet, but I'm sure the time for it will come soon

[@ismailb4334]

I am in the exact same situation. Working on my bachelor thesis, and trying to pipeline my design to reach 50 MHz.

[@messiweltmeista]

@@ismailb4334 are you having issues already with 50Mhz?

[@ismailb4334]

@@messiweltmeista Yes lol, I have a big combinatorial circuit that perform encryption. But I think I will parallelize it now to make the critical path shorter. Where are you from and what do you study?

[@messiweltmeista]

@@ismailb4334 that's really interesting, yes parallelism always helps. I'm from Germany, currently studying electrical engineering

[@ismailb4334]

@@messiweltmeista Also Electrical Engineering here, in TU Delft, the Netherlands

[@zigajavornik1026]

Kind of sad that you stopped making videos. Hope you are doing well!

[@andyhaas5366]

Thanks for the video, but I really hope you follow up with an example of the crossing clock domain timing errors you teased at the beginning. I have that problem, with a 60 and 50 MHz clock trying to pull from the same dp ram.

[@Nandland]

kzbin.info/www/bejne/m6qxhmmjo8Rgbck

[@andyhaas5366]

@@Nandland Thanks. I saw that video, and it's great. But there's a problem specific to timing analysis and clock domains I think, especially if the two frequencies are similar. Would the timing tools not give timing errors if you use stretching and the other techniques you use in that video?

[@shahrzadfeghhi4239]

What tool are you using to do the timing analysis?

[@brad8122]

6:31 before it was using 34 FFlip flops now it is 39. So it did simplify the design?

[@abhijeetchauhan4111]

Do we always need to register the inputs ?

[@fernandoi8958]

Is there a way to place more pipeline stages between the LUT we get after synthesis?

[@Nandland]

You would have to break up the stages further. Here's one idea: shift left is the same as multiply by 2. Shift right one is the same as divide by 2.

[@shawnmirza325]

I did and FPGA design on a xc7a100tcsg324-1 and got it to successfully pass timing in Vivado, then I took this same Vivado project and reassigned the chip to a xc7a100tftg256-1 and my design does not pass timing...... Why would cause this?

[@QuantumDoja]

Hi Russell, My Go Board timing analysis has a "Target Frequency(MHZ)" of 111.36 - but the board should be 25MHZ. Do you know where I can change this in IceCube2? Thanks

[@Nandland]

Sounds like you need to add a .SDC file. Synthesis design constraint. ICEcube is a bit different, the clock gets set in the synthesis constraint file. Most other tools suggest doing it in the P&R constraint file.

[@mikaelsworld6006]

How do you remove timing violation from a large register which is bitwise xored? Example: reg [7196:0] data; Always @(posedge clk) Data_out

[@russellmerrick9761]

Why are you doing a 7000+ bit XOR? That's... large.

[@mikaelsworld6006]

@@russellmerrick9761 it's a requirement of the algorithm.

[@allhero4128]

That the only way to slove this problem ?

[@perakojot6524]

This example is pretty bad because dividing by 3 takes 10x more LUTs than addition and multiplication by 5 (two additions only). So you don't gain anything particularly by splitting addition and multiplication by 5, you only waste FFs.