Generate statement and for loop example in Verilog: A byte-swap in three ways.

[@FPGAsforBeginners]

Two notes! #1, The For loop section starts at 4:00, I realise I was slow on getting there. And #2, the generate statement doesn't generate any code as such, it generates the resulting RTL circuit as if there had been code, to be technical. Thanks, hope you enjoy the video and have a good day!

[@jogeshsingh854]

I'm a fan of your teaching skills :-)

[@FPGAsforBeginners]

Thank you! 😃

[@scottfoerster]

Hi, I am a retired professor. I love what you are doing. Your presentation, your style, your flow is great. I love "iterating over time" versus "iterating in parallel." That set off a bunch of sparks in my brain. Just keep cranking out the video's. The rest of this are the sparks. I am trying to develop an introductory RTL course to replace a traditional GATE course .. now that I have time to do this rather than teach. This is the beginning of the course. I have to start with binary counting. 90% of students will start with 1 rather than 0. Then make a switch turn on an LED. This gets into the board files, and constraints files. Then turning on 16 LEDs on with 16 switches in 16 lines of code. Then one line of code using "down to" concept and linking up with array subscripts in normal programming . After showing the above, the first challenge is for the students to make switch 0 turn on led 15, switch 1 to turn on led 14, etc. I call it crisscross to avoid endianess discussions at this stage of the course. They all turn in 16 lines of code. Then I show them this code ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, module Crisscross( input [15:0] SW, output bit [15:0] LED ); bit [4:0] i; //i has to be large enough to count up to 16 .. not 15:0 .. 5 bits.. 5'b10000 always_comb for (i = 0; i < 16; i = i + 1) LED[i] = SW[15-i]; endmodule ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, It blows their mind. I show the vivado Synthesis schematic. I describe this as "crisscross wires." But this doesn't get at the heart of the conceptual problem they were having. That is why I love your video. What you convinced me of .. is that students are thinking about time. "Iterating over time" versus "iterating in parallel" focuses on time. "Parallel time" is the mystery and I can imagine now how to start a good conversation in the classroom rather than looking at blank expressions and starring at the non-parallel lines above. I try to use the always_comb to emphasize combinatory logic (versus clocked logic) rather than the language synchronous/asynchronous ... at the beginning of the course. And I can't get into parameterization versus generate this early. Just the concept of a module is a struggle at this point. I try to use bit instead of reg. FPGAs internally are two state anyway. The above does generate a bit stream in vivado 2020.2, and physically works on a Nexys4 DDR, but I don't know if this is best practice.

[@FPGAsforBeginners]

Re the binary explanation and counting from 1, I don't know if you've seen my fixed point video. kzbin.info/www/bejne/p33LZJ-GhZ2no7M In this I include a 'fixed point calculator' that I use to visualise how binary works, it also talks about bit indexing, although it's a bit complicated because it does introduce negative bitslicing. The clocked vs synchronus nomenclature I think is an industry/regional difference although certainly clocked/combinitorial is probably more clear for beginners. It's a good point. The regarding the above: For anything more complicated than this, It is usually good practice to register signals into and out of the device right as they come in and go out, and to ensure it meets timing. This is because often the signals will be driven in the FPGA one way or another, and you want those to remain in-sync and meet timing. However in this case the design is so simple, and the FPGA is routing the wires right through from an input to an output without changing them, so for the most part it's fine.

[@fpga-all-day]

Great job! I never used generate statements before so it really helped having someone explain how they work with for loops and why someone would use them.

[@lesvh740]

It appears I confused byte swap and bit reverse. I always thought endian was a bit level operation. Thanks for setting me straight!

[@cheulwoopark-ln4te]

Hello, stacey. I'm a student from Korea, Really thank you for posting such a nice video!!!

[@KK-rg3nj]

thankyou so much this was really helpful, i was struggling to understand how a for loop would make sense in the 'time domain' of verilog but now i get its just replicating the code for simplicity thank you!

[@maninderpalsingh9097]

The good loop

[@eavids128]

Thanks so much for this series!

[@ganauvm270]

wow amazing

[@mathsdbsolver3225]

Even though the inputs at the specified index are corrected in the module, the output sometimes remains indeterminate during the generate loop. Below is the code and its corresponding output. genvar i,j; generate for (i = 0; i < `n1; i = i + 1) begin for (j = 0; j < 2*`n1; j = j + 1) begin if(j

[@NishantKumar-iv9uy]

Hi, www.youtube.com/@FPGAsforBeginners, In the advance level of out assignment, I think there should be some correction, If we follow the above examples. According to me it should be written as "assign out[(NUM_BYTE-i +1)*BYTE_SIZE-1 -:BYTE_SIZE] = in[(i*BYTE_SIZE)-1 -: BYTE_SIZE]". Please correct me if I am wrong! It might be correct If we ignore the previous examples :)

[@tharalpius778]

Hey what if your generate statements dependent on the type of your inputs

[@tharalpius778]

The synthesis shows something wierd I'm stuck on this for so long😢

[@dushantchoudhary7541]

Hello Stacey. Can you please tell me, other than learning an HDL what other subjects should I learn in order to become an FPGA engineer?

[@FPGAsforBeginners]

I've added this question to my list of video ideas because it's a very good one, but the short answer would be primarily Electronics in general. Being a good Electrical Engineer would make you a better FPGA engineer, because understanding how FPGAs work, and how they operate on the board with the other devices will be very helpful. In addition to that, an understanding of the algorithms you're putting on the board. Digital Signal Processing being the big one, and digital electronics in general. fixed point math, boolean algebra, stuff like that. FPGA engineering is quite a broad industry, because you can make the FPGA do pretty much anything, and it can interface to pretty much anything. That's why I like it so much!

[@krishnapalle1637]

Now I understand generate statement 😂

[@ganauvm270]

can you explain the code based on this spec? Write Verilog DUT which generates an output as follows for the given input Input (I): 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,… Output(O): 0,0,0,0,0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,… module two( input wire clk, rst,i, output wire y); Note:  An input ,I, asserts for only one clock cycle.  After the input asserts, then the output should assert 5 cycles later and  Then deassert for another cycle and  then assert again for one cycle.  It is a 101 pattern after 5 cycles  If another pulse on input appears during these 8 cycles output 101 pattern should not be generated for this new input.

[@FPGAsforBeginners]

This looks like a homework assignment. My recommendation is to use a state machine. I'll be doing a video on those in some point.

[@canadianrepublican1185]

You should consider teaching as a job.