Half vs Full Duplex in FPGA & Tri-State Buffer Tutorial

Learn about the difference between half and full duplex communication. I'll give examples of common protocols such as I2C, SPI, UART, and USB, and talk about if they're full or half duplex. Finally I demonstrate how to infer a tristate buffer in both VHDL and Verilog. I demonstrate how those are important to implement half-duplex communication
Please help me keep creating great content. Support me on Patreon:
/ nandland
Also get yourself an FPGA board, The Go Board, so you can try this code on your own.
www.nandland.com/goboard/intr...

[@bamsgian9759]

That's clear explaination, Thank you.

[@LandBoardsLLC]

SPI with a single master and single slave device is sort of full duplex, but when you have multiple SPI slaves you have the same issue with the MISO line. Each SPI device has to be tristated from the SPI until it is addressed with it's own Chip Select. So it's really not any different in design practice from I2C or any other bus where the slave transmit (to master) line has to be tristated.

[@tariqhada4534]

But i think is CS' =1 then chip will not be selected in that case doesn't matter we choose tristated buffer lines or normal ones 🤔

[@olekristianrannekleiv762]

if Rx is connected to the Tx, why do half duplex hubs need crossover cables between each other? it looks like half duplex only uses Tx for transmission? would it not then make sence to only use straight through cables regardless?

[@michellenicholes2087]

I have a friend who says this is not correct for I2C which is an open drain system. We googled what is the difference between Tristate and open drain and it says something about current that the open drain does not allow any current. My friend says that is why the tristate does not work for I2C. Please help me understand if my friend is correct or not.

[@karenwinchestermex]

Where's the beard? :(