How to Define Different Clearance for Internal and External Layers

[@jajaveve4638]

Take a look on 2:06, when Checking if the Rule on the Mid Layer is working its clearly visible that the polygon is poured with new clearance to the signal lines BUT not to the Via's ....

[@superjimnz]

There are nasty fish-hooks with this; multi-layer objects are not in the scope of the "OnLayer" method for all copper layers like one might expect. Instead the "ExistsOn" method has to be used for the intended results.

[@_ATHONOR]

THANKYOU!! Saved me and my colleague several days on a Space Board wondering why our inner padstack clearances were failing DFM review but passing DRC. Good day to you sir 👍🏻 I will make sure to pass the batten of Altium Software Issues further down the KZbin comment section.

[@riccardoruffo6101]

Not working.