How to do Clock Net Shielding?? Learn @ Udemy- VLSI Academy

The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.
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[@ramesh355]

What is global skew and target skew? How we will deside those values and what is the importance in the design?

[@coastalfly5508]

Clock shielding can impact on hold?

[@vishesh12345007]

please correct me if i am wrong. The delta delay is at net and not the cell delay and its equivalent waveform is used and hence delay calc is done at the 1.5 stage delay.

[@VLSISystemDesign]

Delta delay is on net. You are right

[@vishesh12345007]

thanks.

[@lexiweasly7245]

1)Clock Net Shieldling 2) Timing analysis (with real clock)