Thank you Sir! Please upload more on complex layouts.
@rubenbosch3831 Жыл бұрын
I loved the video, could you upload a video where a typical exam is solved? For example: Given the layout of the figure, it is requested: a) Bar diagram. b) Diagram with transistor symbols. c) Circuit operation table indicating, for all possible combinations of its inputs, the state of the transistors, conducting network and its equivalent resistance, logic value at the exit. Indicate the expression of the logical function performed by the circuit. d) Assuming that a capacitance of 0.01pF is connected to the output, find the maximum delay produced by the gate and for what type of transition it occurs. Data: Rp = 3kΩ, Rn = 1kΩ.? ......
@wssz1123 жыл бұрын
nice explanation and like your voice too :)
@Prince_62992 жыл бұрын
Thank you so much for this video! It helps me a lot!
@malcolmdinz19125 жыл бұрын
thanks for the clear and concise video!
@yhyquyАй бұрын
Thanks❤You help us.
@Jas_011017 жыл бұрын
How do you know the transistors on the left are PMOS?
@Dawntech7 жыл бұрын
left? All the transistors in the upside are PMOS and all transistors in the downside are NMOS because the circuit was building using a complementary logic with Pull Up (PMOS transistors) and Pull Down (NMOS transistors).
@dimitarzhekov95505 жыл бұрын
PMOS body needs to be connected to VDD in order to be properly biased so it makes sense to be on the top
@S_P_S3 жыл бұрын
Can you make this kind of video? Your videos are really great.
@dianajeebful6 жыл бұрын
Thank you, this was helpful.
@mhamedhamadaembaby25023 жыл бұрын
Thank u sir, but can you help me in solving such circuit
@shrushtitripathi38733 ай бұрын
Thanks a lot sir
@atiqwanumar43265 жыл бұрын
correct me if im wrong sir. from the pmos logic you found, you just can do the opposite for the nmos. is it applicable for all circuit if we only just opposite the pmos to get the nmos? thanks in advance sir.