Introduction to FPGA Part 5 - Finite State Machines | Digi-Key Electronics

[@AhmadAsmndr]

I just entered the 2022 watching your video and I want to wish you a happy new year. One of my main goals for the new year is to learn FPGA, and I am going to achieve it with your help. From all my heart, thank you.

[@EmulationOnline]

Nice videos! One nitpick: usually the toggling of a button after pressing is called "bounce", which is why you want to "debounce" to remove the flicker.

[@ibrahimalikadawa5011]

Very good job, Shawn. You have done it so much that we have to say thanks! The series is found very helpful. Keep it up please.

[@ShawnHymel]

Thank you! I'm really glad you are enjoying the series!

[@rjordans]

Another thing to note for the mealy machine is that the outputs can sometimes show glitches when the output is triggered upon entering the state even though the input value changes and the next state doesn't go along the edge that had the outfit value specified that you saw

[@0LoneTech]

When using non-blocking assignment, you do know that whatever value you read within that always block is the old value (or rather, current; the assigned value appears in the future). If using blocking assignment it will read sequentially within that block, much like in common (sequential imperative) programming languages, but it's easier to lose track of what the actual logic is then (longer sequential code can create complex deep logic).

[@ShawnHymel]

Thanks for the heads up! I did my best to give examples of blocking vs. non-blocking assignments at 13:16.

[@RebelCoderX]

Challenge SPOILER: I made the debouncer using only 2 states, but I'm using the delay counter itself as a kind of sub state.. Only when it reached the maximum value, I test for the button input value, when that is high while the current state is "released" then I reset the delay counter, increase the ledCounter output and change the state to "pressed". Then when pressed is the current state, I test if the button input is 0 when the counter has reached the maximum value. In both states, when the counter has not reached the maximum value, I just increase the delayCounter value by one.

[@TinLethax]

Great video Shawn !

[@vaniaeli4392]

Muito Obrigado por democratizar esse conhecimento ❤

[@seankayll9017]

This is a great series, thanks for making these. Just a quick question if I may, at 16:38 could one also write "always @ ( state ) begin" to make it more obvious which signal was the trigger? ed. Yes I know a good teacher would say "try it and see" but I haven't had the chance to set up my shiny new IceStick yet!

[@ShawnHymel]

Yes, the ( * ) sensitivity list should tell the synthesis tool to run that always block when (state) changes.

[@alexandrsavochkin9442]

Thanks, Shawn, for the great job, your tutorials helped me to start with FPGAs. I am wondering if the behavior described is well defined: There are 2 always blocks triggered by positive clk edge, so I assume they are executed simultaneously. One block increments clk_count and another block compares it with MAX_CLK_COUNT. Can we do it simultaneously and is it well defined behavior? Are there any chances that comparison will happen before increment in one clc cycle and after increment in the next cycle so we will miss the MAX_CLK_COUNT condition?

[@matthewprater7892]

Great video! When I run verify, i get an error with the done_sig both times they are used in the code (fsm-moore.v:115: error: done_sig is not a valid l-value in fsm_moore.) for both moore and mealy approaches but the error goes away for the build and it uploads fine. Also, unlike file names, verilog does not like dashes (-) in module names

[@byronwatkins2565]

At 22:20, one bit can have only two values, so you don't need a default either.

[@ShawnHymel]

Good catch, thanks! I have a habit of always putting default cases, even if the state can't ever physically get there :)

[@byronwatkins2565]

@@ShawnHymel That is a good habit and the compiler probably would generate no extra code.

[@MR-fs2pc]

Out of interest, would default catch the X initial value of state? It seems to in simulation, but I am not sure if it would in reality.

[@byronwatkins2565]

@@MR-fs2pc Real bits are 1, 0, or in transition. The simulation you mention is not synthesizable.

[@katemoon7476]

This probably isn't the right place to ask, but does anyone know of any expos, conferences or trade shows for embedded systems in the US for 2022? Anything regarding the PI, Beaglebone, embedded systems, PCB's, hardware or similar.

[@JeffreyBaker-es3ej]

Hi y'all! I can't get apio to recognize the device "ftdi_usb_get_strings failed: -4 (libusb_open() failed)". I've followed the instructions to the letter, tried changing to the libusbK drivers to no avail. The default FTDIBUS drivers also failed. Also, the device added to the device manager isn't as shown, it pops up as Dual RS232-HS (Interface 0) and Dual RS232-HS (Interface 1). Changing one or the other, or both to libusbK fails any which way. HELP or I'll just forget this toolchain and tutorial. ):

[@razvanvlad607]

Can anybody help me? I'm a beginner and I'm looking for a FPGA board to start with. I don't know which board is the most suitable for me. Nexys A7 is way too expensive. My options for the time being are: Basys 3 artix-7, Arty A7/S7 or Cmod A7/S7 (breadboardable). I need a good price quality ratio. And also I don't know if the breadboardable boards are enough powerful and capable. Are they worth it? Or the extra money for the other boards like Basys and Arty is worth it more? Thank you very much!

[@fredkilner2299]

Hey was anybody at the first West Coast Computer Faire at the SF Civic Auditorium in 1977? Did anybody see me? I was starving and I saw a hotdog for 45 or so cents. Crazy!!! Next time I was there I saw U2 in high school. A few years later I was at a West Coat Computer Faire at the Moscone Center. There was a guy who had red hair who came in to Computer Land of Los Altos in a wheel chair and I saw him up there at the Computer Faire. Apple ][ was my favorite! Woz's integer basic was fast enough for vid games. I wrote a lo-res graphics missile command game which was fine but Microcraps Floating Basic was so slow it sucks slowly. At Computer Land they put the Apple ][ where the Compu Color used to sit. Yesterday I wore my ASR-35 teletype shirt at Cosco and the guy who always asked us if we were a super member or something thought he had been tortured by those. As a super youngling one of my friends brought me to some room full of those and he showed he had turned off the echo or something to save it printing. He told me I got him into computers and I can't remember why but I always loved computers but my generation had the most brain dead adults because it was always going against the grain. As a kid it was good there were so many Chinese, Vietnamese and others who were normal, because there were so many I dunno what they were lazy people who wouldn't do their math or anything work.

[@embeddedbastler6406]

Hmm, one should really not use an output of a flip flop as a clock for another flip flop, as this can cause some nasty timing errors. You should use a clock enable signal instead.

[@ShawnHymel]

Now that I'm looking into metastability and cross-clock domains, I can see why this might be an issue. However, all of the resources I come across for creating a "clock divider" use the output of one flip-flop to clock other flip-flops. Do you have any suggestions or resources that show how to create better clock dividers?

[@embeddedbastler6406]

@@ShawnHymel I think nandland explains it well in this video @ 9:30 kzbin.info/www/bejne/nqXanZVjedp4gZo

[@ShawnHymel]

@@embeddedbastler6406 Thanks! It seems that using the output of a FF as a clock signal is a naive approach that's used in a lot of books, content, etc. While it makes sense for beginners, I can see why it could cause issues. I plan to mention this in a future episode (along with why it's bad) and offer a better clock divider example.

[@b213videoz]

9:13 Hey man, Python doesn't have SWITCH/CASE statement though 😁🤣

[@surflaweb]

This is NASA code.

[@rjordans]

NASA would probably use VHDL though

[@Jkauppa]

prioritized tasks, as you dont need to do work that is not needed, better have food than have nothing served

[@Jkauppa]

language makes things very hard

[@Jkauppa]

its not very efficient in delivering the intent of your design, its tech talk

[@Jkauppa]

it should be "do this" instead of "you need to do this and this and this and this"

[@Jkauppa]

your unnecessary complication hides the thing its doing, you cant see the forest from the trees (statements), and documentation is a chore, not a blessing, make it simpler to both convey the meaning, intent and the implementation in same package, visually

[@Jkauppa]

for "gods sake" have it at least object oriented, not this statement litany

[@mofear4874]

all wrong