IO pad placement | .io file writing | pad placement in Physical design flow

[@patinagreene9070]

You have an excellent and very detailed explanation of IO assignment file format. I've had some difficulty getting Innovus to accept my .io file and the video helped quite a bit. In particular the clarifying the nuances like: Why the corner cells must be oriented a specific way [I thought if you rotated a square 90deg, you'd get another square, but that's not exactly true, as you pointed out], and: Where the value of parameters such as total_edge come from. Nice work - Thank You.

[@TeamVLSI]

Thanks a lot @Patina. If possible try to help us to reach these video to maximum people of same mindset. Keep learning! Keep sharing!!

[@karrarhussain776]

Simple and Clear explanation. Good

[@TeamVLSI]

Thanks Karrar ! :)

[@sridharchandrasekar7787]

Sir, nice explanation...

[@stevenlian7748]

Thanks a lot for the video, very clear of each step. Quick question, if we are adding pad connection in the verilog file, what about the power wire connection, since power wires are not specified in verilog files? Thanks a lot! Adding another one here, does the top module still contain inputs and outputs, as it already contains both pads and the core? Thx!

[@TeamVLSI]

Welcome @Steven Thanks for your appreciation. power nets will connected automatically. Not clear about the second question.

[@niranjanreddy2637]

If I want to create io power pads , how to create io power pads Is there any command to create io pads

[@karimshahbazi5338]

Thanks a lot for your nice learning clip. Unfortunately, I am facing errors in defining Cell names. Where can I find the Cell names in my LEF file?

[@TeamVLSI]

Yes, you can fine in LEF.

[@rohanyadala9096]

Very nice...

[@bluehive2501]

Thanks for your video it was verry helpfull! Quick question: How can I connect my design output to the IOpad? P&R process creat Pin for the design output instead of connect to IOPad...

[@TeamVLSI]

Hi @Blue, You have to make changes in netlist.

[@bluehive2501]

@@TeamVLSI Thanks for your answer, could you provide me an exemple ?

[@Shiva-ju2ct]

How we supply power to each pad

[@Shiva-ju2ct]

And how we connect eachother

[@saikanthand.l.1598]

what's the use of corner cells ?

[@TeamVLSI]

One is to provide VDD and VSS continuity.

[@officialananthanm6545]

For me corner cells are not found.. I have double checked the .io file..syntax is okay..

[@hemalakshmi985]

sir how to do the IO PAD or IO PIN Placement in floorplan stage??

[@TeamVLSI]

Thnaks Hema, You can do pin placement at floorplan stage and this is the conman way. You can use incremental pin placement method. For example, in IC Compiler there are commands set_fp_pin_constraints ... -pins [get_pins ...] -incremental on place_fp_pins which will place pins as per your constraints. You may read more about this in Solvenet. OR you can search "pin placement" on user guide of Innovus.

[@StayInBliss]

sir pls give us idea about icc

[@TeamVLSI]

Hi Anish Actually IC Compiler is a similar place and route tool of Synopsys like Innovus of Cadence. All the concepts of P&R will be same just there are some difference of commands in ICC. You can refer the ICC tool commands manual for more details.