Design Import | Cadence Innovus | GUI of Innovus | Cadence innovus tutorial

This is session-9 of the RTL-to-GDSII flow series of the video tutorial. In this session, we will discuss the various fields of design import setup. We can import the design directly through tcl script also but here for a better demonstration of the various files required, during the design import we used GUI interface. Once we import the design file we can save one global file and letter we can directly load the saved global file. The detailed flow we will see when we will do the hands-on on the innovus tool. In the next session, we run the complete PnR flow using the script, and then after that, we will perform the PnR in GUI mode.
In this RTL-to-GDSII flow video series, there are total of 10 sessions. We have covered all the stages of ASIC design using EDA tools demonstration and also the basic theories. Part-wise descriptions of the different session and the link of videos are as follow.
1. Session-1: Overview of RTL to GDSII flow | Basic terms in the flow
Video link: • RTL to GDSII flow | Ba...
2. Session-2: Flow in EDA tool's perspective | Different EDA tools | various files
Video link: • ASIC Flow and EDA tool...
3. Session-3: Functional verification of RTL | using Synopsys VCS | VCS demo
Video link: • RTL Design & Simulatio...
4. Session-4: Logic Synthesis flow | RTL to gate-level netlist | Design compiler
Video link: • Logic Synthesis flow |...
5. Session-5: Logic Synthesis | Design Compiler | Command-line | gate-level netlist
Video link: • Logic Synthesis of RTL...
6. Session-6: Logic Synthesis | Design Compiler | GUI Mode| design_vision
Video link: • Logic Synthesis in Des...
7. Session-7: Logic Equivalence Check using Formality |S8| RTL-to-GDSII flow | Formality tutorial
Video link: • Logic Equivalence Chec...
8. Session-8: Physical Design Flow | PnR flow |RTL-to-GDSII flow | innovus flow
Video link: • Physical Design Flow |...
9. Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial
Video link: • Design Import | Cadenc...
10.Session-10: Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo
Video link: • Place and Route in Cad...
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[@byambajavr6519]

Very good explanatation sir.

[@TeamVLSI]

Thanks

[@chandrakalarouthu1739]

Thanks you soo much sir it is help full for the self learners

[@TeamVLSI]

You are welcome Chandrakala. :) Stay tune to our channel and blog for more such learnings!!!

[@chandrakalarouthu1739]

Sure sir

[@snkhy5631]

thank you sir

[@amleshkumar6255]

Hi, Thanks for explanation. If I have only LEF/DEF file from OpenAccess Public platform, could you tell me how can I import/use it in Innovus tools or any other tools or any other ways? Thank you in Advance

[@TeamVLSI]

Hi Amlesh, I couldn't understand your query clearly. could you please explain it.

[@amleshkumar6255]

Hi , I don't have any library, .db & IO file. I have only LEF/DEF file. How can I use it in innovus tools?

[@TeamVLSI]

Amlesh, You can't use LEF/DEF stand alone.

[@amleshkumar6255]

Hi, Thanks for reply. how to get other required files to use it Innovus? Could you help me to get it?

[@TeamVLSI]

Your organization should have to sign an NDA with the distributor of PDK. Ask to your HOD or concerned authorities.

[@rishovaditya7452]

How can colleges acquire licenses of Synopsys Hspice? If you can provide some information regarding this, it would be great.

[@TeamVLSI]

Rishov, these licences are industry standard licences and very expansive. So You have to be a part of any good research organisations which have these licences or VLSI Industry.

[@TeamVLSI]

Ohh Sorry, You are talking about colleges, So now all the IITs NITs and IIITs have the licences under SMDP-C2SD project. In case of private Institution, they have to invest money for that. They can directly contact EDA tool vendors and buy the licences as per requirement. For more details mail me, I will provide the contact of vendors

[@avinashk5510]

Please make videos on PT (STA)

[@TeamVLSI]

Ok, I will do that.