ISA 1.3 Registers and memory: MIPS Memory Organization

[@Ricky-zc8qm]

Dude seriously this is the best tutorial. I've been searching for days now to find a video that explained how registers, RAM, and opcode all worked together, this series was the best. Repped +1

[@elliott8175]

Yeah, I wish I could upvote this more.

[@Zeddy27182]

This is the BEST video EVER!! I was lost during the class, but NOW I totally understand the whole concept. Thank you so much, Dr. Black-Schaffer🙏 I wish you had other CS lectures.🥺

[@MinhLe-xk5rm]

shit man i wish i had discovered your video sooner, rather than 1 day before my system architecture midterm :(

[@ridwankhalid2826]

Hard relate.

[@abdullahazmat7693]

Me here 1 day before final term 😃

[@97PSY]

Thanks so much this video is simple enough for those who need help to understand and informative enough to reach understanding. This saved my life.

[@EL-wd4lb]

This video series is saving me, especially since I have a horrible teacher. Great work!

[@avelaonkenyathela2039]

Dude with these series of videos, you really saving my life MuchAppreciated

[@adrianjuszczak298]

Aaaaaaamazing job! I wish I had teacher as you!

[@maxcaulfield9645]

You're a God send. I have a pretty terrible professor and equally terrible textbook, but this helped so much! Thank you!

[@ashleylove6840]

How the HELL did you just do that, you cleared everything and I suscribed, love you man and thank you for what you do

[@joonauutela581]

This is the best thing since sliced bread... seriously. amazing job man

[@fleabug91]

Thank you so much! My teacher had me so confused!

[@estherning5773]

best vid about mips in the world

[@SakuraEvangeline]

This was such a good video, thank you so so much! I thought I had already understood most of those things in our lecture, but you proved me wrong (and helped me actually understand it :D)

[@Jar-eg2jx]

Thank you so much! You just made my day

[@sammylish1]

Very helpful series and visualisation ! TYSM

[@yunni7817]

thanks so much!!! finally understood how it works.

[@happylogoblock]

You are the Best! Thanks for making this video

[@tula1308]

Best tutorial ever

[@musnathilahi]

It's very good tutorial.. Thank you very much

[@user-cvviwion]

Nice balanced, intuitive lecture.

[@angelgiovanis3188]

this is very helpful thank you very much

[@hesahesa5665]

Thank you very much

[@hindachniri6909]

thank you so much! you're the best

[@ΙωάννηςΑποστολίδης-σ3σ]

Thank you so much! Allow me though to wander why the big memory is reasonable to be slower, due to bigger length of address and time to reference a cell maybe?

[@realmajumdar]

word is 16 bits, doubleword is 32 bits... correct me if I'm wrong

[@aymansleem7565]

you are right ...BYTE IS 8 BITS AND WORD IS 16 BITS AND DWORD IS 32 BITS AND QWORD IS 64BITS OF BINARY DATA NUMBERS REPRESENTATION and each of that binary number width can represent close to unlimited number patterns

[@srinaath9845]

Thank so much man.It is so helpful.Great job.

[@donnydunno9346]

The tutorial is brilliant

[@omrcm]

it's a greate work. thanks...

[@mijaelrodriguezsaavedra2615]

so good! Thanks!

[@amanpreetkaur1738]

soo good💯💯

[@manslayerpupil]

You are a life saver

[@朱祥誠]

Nice !

[@sharanv9182]

thank you i understand now how it works

[@kpax9284]

isnt it possible to adress a specifc byte within a word? For example with the unaligned adress from the 9th Byte we could adress the 9th byte directly with byte-enable-signals which is made of the unused bit A0 and A1?

[@xchaoticmindx]

THANK YOUUUU!

[@abdullaha2585]

Thank you very much :)

[@jjww2788]

Thank you soooo much

[@maryta22]

Gracias :)

[@wahalaq36]

Nice work!!

[@md.al-amin9851]

please upload complete video like this(ISA) based on ALU, compter performance, datapath and control, pipelining, cache & virtual memory . please sir

[@shabushafi2107]

great explanation. could you please share the slide. it will help a lot

[@salmaeasa1567]

Thanks

[@leoxu4238]

Thanks!

[@jyothyar3800]

which book you prefer to learn MIPS

[@selmanemohamed5146]

thanks for the very helpful video but is this the mips r3000 i want help please

[@louisferreira9055]

Hi David. Great video series! With regard this particular video, I fully understand your explanation of memory access.However, I'm questioning the practicality of this from a hardware perspective. For example, lets look at the load word instruction (LW $d, $s, $s)... Lets assume that the program counter is currently pointing to memory location 4, and the current instruction is load word with parameters reading the data at location 4 into register $d. Because the memory is only 1 byte (8 bits), this execution will will only return 1 byte into $d (because we are only referencing 1 position of memory... namely position 4). So how does the hardware perform the next 3 reads (memory positions 5, 6 & 7) to make up the 4 byte word? Surely this would require that the LW instruction be split into 4 LB (load byte) instructions over 4 clock cycles?

[@pontuslundstrom5831]

Probably a bit late for Louis but if anyone else happens to stumble on this, here's my shot at an answer: the concepts "word" and "word size" (the number of bits in a word) are really key here. Generally, the natural unit of data of a CPU is the word, not the byte (unless, of course, we're talking about an 8-bit CPU). Thus, from the point of view of the CPU, "byte" it is not that useful of a concept. The Wikipedia article "Word (computer architecture)" goes into the gory details of various architectures on this. To the question regarding the LW and LB instructions, I don't know the low-level implementation details of MIPS, but I would guess that the instructions that load or store less than 32 bits (LB, LBU, SB, LH, LHU, SH, etc.) all still use the full 32-bit memory bus. Again a guess, but it seems to me that the irrelevant bits need to be masked in hardware (n.b. the sub-32-bit signed loads also need additional logic gates to do the sign extension).

[@dalinsixtus7648]

Sir MIPS is byte addressable not word addressable

[@hrithiklanghi6418]

But the 0 address byte will have address 0000 0000 So 0,1,2,3 bytes in one word so last two bits should be 11 right??

[@shivangs11]

Being a 32 - bit processor has nothing to do with the size of memory. It is the address bus size which defines the number of addressable locations eg: 8086 is a 16 bit processor with 20 bit address bus which allows it to support 1 Megabyte of memory.

[@kachiuli]

where can I find the slides of the video?

[@jocampe62]

3 days left for the Computer Organization exam monkaS

[@FelipeCampelo0]

Didn’t know memory is 1B while the registers are 4B

[@mudabirsadeed3716]

+1

[@ahmetkarakartal9563]

thank you so much

[@بسامحسن-د4ث]

Thanks!