JK Flip Flop in Xilinx using Verilog/VHDL | VLSI by Engineering Funda

[@EngineeringFunda]

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[@EngineeringFunda]

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[@mybluepan8675]

Very good playlist. These are the skills which makes you engineer and gets you job. Sadly it has very less no. Of views.

[@EngineeringFunda]

Your positive comments motivates me, Thanks and welcome 🙏

[@sidhantawasthi1259]

please upload more on xylinx . very helpfull it is

[@EngineeringFunda]

I have planned another 12 videos

[@sudhanvagr]

We can use test bench waveform too to give input and check output instead of writing another small piece of code.

[@Niteshkumar_-ee3dh]

What will happen when j & k both are 00? Do this circuit create latch for undefined case?

[@adilakammadath1200]

Sir , pls upload modelling of counters in verilog

[@sirishaaluri6239]

Sir is this complete playlist is useful to get job in VLSI fomain please give me rply sor it means a lot for me

[@EngineeringFunda]

It gives understanding of basics of VLSI which is useful to start your study on VLSI. Yeah to get job this is very important playlist.

[@icecoldnobody3447]

is this 4 bit?