JK Flip Flops

A video by Jim Pytel for renewable energy technology students at Columbia Gorge Community College.

[@PaulR387]

Thankyou Jim for sharing this wealth of knowledge for those who cannot attend college or universities, god bless you friend.

[@Nadrealis]

I'm going to be faving all of your vids and liking them, I learn so much from them.

[@esparda07]

Thank you so much for this sir. I have a not so good teacher and I really needed this. Thank you again.

[@suzyprincen3443]

You are the best!! Greetings Ben from Belgium.

[@carln22]

With highest respect sir, i have watched some of your other videos too and they're ALL CRYSTAL CLEAR. Thanks for sharing this.

[@Rida9651]

JIM YOU ARE MADE OF AWESOME!

[@belalafghan]

Thank you very much, you explain it way better than our teacher !

[@91418300]

Great video! Thank you very much.

[@TheSuperRunner]

In this situation, both of the 3 input NAND gates will actually be outputting 1, which means that the latch is going to stay set. If J is putting in 0, clock is putting in 1, but Q' is putting in 0, then that gate's output is 1. On the other side, if K is putting in 0, clock is putting in one, and Q is putting in 1, then that gate is also 1. Therefore, the latch stays set.

[@ClownDatWalk]

Alright, now that i found this awesome Jim, i can skip my lectures :D

[@MelodicMetalist]

I'm leaving univerrsity right away, it's no damn use! I watch you all the time to clear my doubts haha, you're the BEST

[@unknown256888]

just wanted to say that u helped me pass my electronics course thanks alot :D

[@viktor133100]

a device that detects the rising / falling edge of a pulse instead of the pulse itself and gives a 1 value on this edge. the edge of a pulse takes far less time, thus allowing synchronistion problems to be avoided in applications

[@ranfeamon]

You are awsome!!!

[@MohamedSHbib]

All the explanation was consistent, some one is trying to say that at 11:35 minute, the JK should stay SET, but that is not the case. It should, as Prof. Jim Pytel has said, go to RESET mode. Nice!!

[@karthikm.d291]

thanks man...u r gr8

[@hirromzero1]

thank you! I finally understand this

[@XtreamSJ]

prof = useless mono digital logic design text = not so useful but you made this crystal clear thanks !!

[@jaredtaibi9104]

Hi, I'm a student at Thaddeus Stevens College of Technology in Lancaster,PA and wouldn't be easier to introduce the clock after the SR Latch and introduce it by useing the Edge-triggered D flip-flop

[@vazreab]

great explanation! Thank you.....

[@akioshun]

Great lecture, just in time for my tutorial later. :)

[@karimkhan1312]

this is excellent-- i do not under asynchorous -- pls explain meaning of asynchoronous

[@XzcutioneR2]

I finally got how this shit works, THanks :)

[@motaz920]

GREAT!! JUST BRILLIANT!!

[@indago9]

I clicked at 9:35 Great Tutorial! Please make more :D

[@zhaoflyaway1015]

thx, it's great

[@Altair9292]

What if you have an active low preset in between the rising edge clock signals? Would that affect Q, or is that only when the active low preset occurs during a rising edge clock signal?

[@PooleH]

If only I was going fishing and smoking with Johnny Loco instead

[@rodwynnejones]

In toggle mode, how long (or short) can the clock pulse be, e.g. can a push-button be used to toggle and held down for any length to time (assume switch de-bounce implemented) or does it need a pulse that is shorter than the propagation delay?

[@MusicAddictedGr]

thank's for the video but i need some help... how can i make the clock? just a +5V or do i need pulse generator?

[@mdude911]

Any reason why you started out with an active low SR latch?

[@XtreamSJ]

what is the textbook you are using ??? like the example 7 is coming from what text?

[@KoreaRwkz]

Can someone explain to me how there's no situation where S' and R' are not simultaneously set and reset? Because if the output of J and K are 0, and Q is assumed to be 1, then Q and Q' will both be 1, which is the invalid mode.

[@KennyKoller]

If I had invented this device it would a K-K Flip Flop--only useful for toggling.

[@jlmknight]

thank you :)

[@nychulo7]

WROING!!!! Minute 11:35 J 0 K1 Current State Q 1... should state in in 1. Look at basic SR when S1 R 0 it sets to 1.

[@strobe007]

I owe this man a pint

[@david1575cm7]

Great vid thanks!!

[@justinm410]

It's named after Jack Kilby, he didn't invent it actually.

[@quiquinnn]

Could explain me how can I build a FF T? I want to divide frequency using that. Your videos are very helpful thanks

[@dookiebabii]

love you man

[@DrTomb]

Can I download This video?

[@hemaraj4550]

"preety cool uh " i like the way u say it ,anyway thx for this vid nw i got no prob wif jk flip flop :)

[@nychulo7]

Wrong minute 11:35 when j0 k1 current stat 1 should stay in 1. look at basic sr latch when set 1 r 0 it sets to 1 !!!

[@debadyuti7]

where is the characteristics equation and table where is the excitation table and equation

[@alikhan-cw1gl]

great

[@checkwattpad]

i want to fire my professor and hire you.. i love you.. haha..

[@011azr]

pretty cool, huh. LOL xD.

[@indago9]

I was looking for minecraft :D

[@mouhaahaahaa]

what's the difference between blind and VERY blind? nothing to me.

[@Dpfpv1]

Toogle heh

[@zan9815]

1 man is VERY blind

[@FlamingFox5]

...

[@Xinthose]

I don't understand this stuff; fail

[@JimTaylor42]

Nit-picker. I suppose you nave never made a mistake.

[@MusicAddictedGr]

thank's for the video but i need some help... how can i make the clock? just a +5V or do i need pulse generator?