Tutorial 1: Verilog code of Half adder in structural level of abstraction

[@Chandanyadav-dl9kz]

Sir you are the best explainer!!

[@HarshithaGowda-g2n]

o

[@aryanpanchal9248]

thank you for this awesome video, i really appreciate your efforts sir!

[@surajitdas2505]

Thank you very much for the awesome tutorial

[@knowledgeunlimited]

You are welcome

[@richman3111]

Thank you! Great video.

[@nikilnikki18]

How to install this software for

[@bennguyen1313]

Would love to know the history behind Enjoy-Digital , Catherine/Whitequark and AmaranthHDL. From what I understand, Travis Goodspeed originally commissioned Enjoy-Digital to make LiteX, which is described in Migen... this later became nMigen, but seems this now has a fork to Amaranth HDL... and there seems to be a dispute in the M-Labs and whitequark (former affiliate of M-Labs?) over the direction/brand of nMigen. Also, any thoughts how it compares to Chisel or Spinal HDL? Any thoughts on PyHDI/Pyverilog/PyVHDL/pyHDI? For example isn't VexRiscv for litex written in SpinalHDL? I'd like to do an SoC based design for a Trenz SMF2000 board.. using either LambdaSoc (Amaranth HDL) or LiteX (m-labs or whitequark's Migen/MiSoc). Ideally, I'd like to leverage off-the-shelf IPs (litescope, , ValentyUSB, minerva or VexRiscV). The goal is a bridge that allows a CPU master to access AHB-Lite and APB3 slaves, all from the Cortex-M3's AHB Fabric-Interface-Controller. (BTW, there's a great blog post on CrowdSupply for Cynthion titled "Moondancer: A Facedancer backend for Cynthion") Also, the debugging tools available for software development have become very sophisticated.. with advanced breakpoint capability, stepping, realt-time variable watching (swv), etc.. with HDLs, it seems the process of debugging hasn't changed and still requires manually writing thousands of test-benches! (Altera's old Max+Plus II Waveform Editor you can could draw your waveforms, then simulate!) Do you know if there's been any development in the area debugging of logic? Everything I've seen still uses test-benches (Icarus Verilog, Verilator/signalflip-js, Aldec Active-HDL, Metrics Cloud Simulator, GHDL for VHDL)!

[@RTL_Coder4u]

sir can u pls explain this ...how can we design comparator(2 bit) using mux

[@alurunagireddy652]

How to download software sir

[@rakesh_007]

sir in test bench , for waveforms ($dumpfile , $dumpvars ) are used right . but you did'nt wrote it,how waveforms are generated??🤷‍♂️

[@knowledgeunlimited]

In this simulator not required.

[@rakesh_007]

@@knowledgeunlimited okay sir

[@madhavareddyketha6688]

Is it necessary to write the test bench for simulation ?

[@knowledgeunlimited]

Yes, unless you give test vector's how can you check output.

[@VarshaSonyHasan]

This is too nice

[@TheGujjuFlute]

Please help , I don't do simulate behaviour models for DFT What can I do..???

[@ganauvm270]

Hi you explain up-down counter using fsm

[@shrishtiswaraj3797]

Sir which software is installed for verilog?

[@dailyanimedoses6999]

xilin vivado

[@VickyKumar-fw5qr]

Which software is used in these videos

[@aspirin4709]

What version is the software sir?

[@Patirko123]

Sir, kaun sa software use kar rahe ho ? Please reply 🙏

[@knowledgeunlimited]

Xilinx windows supported version of tool

[@Patirko123]

@@knowledgeunlimited okay

[@priyapatle5252]

Which software have you used for verilog coding.May you tell me the name of the software?

[@brixenmathis6536]

he is using xilinx vivado in this video.

[@henryzuniga7111]

Where do you download software?

[@dailyanimedoses6999]

xilinx vivado

[@bezaljohn8787]

how can i do this in macbook??

[@ParthVerma-kc1wr]

@bennybutler1267 😂😂😂

[@anus5965]

Sir software name and it's installation please

[@knowledgeunlimited]

Xilinx ISE design suite.

[@matambasavaraju3430]

@@knowledgeunlimited is it free

[@knowledgeunlimited]

@@matambasavaraju3430 yes

[@bharathisesham]

​@@knowledgeunlimited sir how to install could u please explain

[@addielvega]

This is behavioral implementation not structural. Behavioral Verilog describes the functionality or behavior of a digital circuit without specifying its internal structure. Structural implementation you are describing the internal structure of the circuit.

[@spacevideos121]

chutya tutorial

[@Ibrahim.gaming]

😂