Lecture 05: Architecture of ARM Microcontroller (Part II)

[@alexroman665]

Wow! Bless this guy... good pipeline explanation. And want to say thank you for this initiative.

[@socialogic9777]

ansolutely true

[@jaysiddhapura]

One of the best explanation or pipelining !

[@vennapoosahemanthkumarredd5530]

In throughput calculation the denominator (total time taken is ((k-1)+N)t ).

[@deepakmanishvar]

👍👍👍

[@jagatpatiraiguru9806]

Thank u sir

[@Rajatsharma-lx8og]

Thanks

[@dhaneshprabhu72]

Why do we need multiple clk cycles for parallel loading ig registers,using PISO(parallel in serial out) register it can be done in 1 clk cycle. Please someone answer this for me,they will be blessed.

[@swastikkhuntia3283]

But why, I mean it's serial out right, so we require 1 clock cycle to parallely load the shift register and N clock cycles to get the actual output serially. So I don't think that would help.

[@WillhemCrool]

27:19

[@pritambharti2474]

why forcibly you have translated in Hindi, where to watch the video in English

[@pritambharti2474]

got it

[@raghavchakravorthy3896]

is there any link for download PDF file of this lecture

[@ishanagarwal475]

Go to nptel you will find it there.