Lecture 21: Main Memory and the DRAM System - Carnegie Mellon - Comp. Arch. 2015 - Onur Mutlu

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Carnegie Mellon Computer Architecture

Carnegie Mellon Computer Architecture

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Пікірлер: 14
@tvcharan
@tvcharan 9 жыл бұрын
Amazing Lectures!!! Thank you for making it public. Hope some day will listen to your live lecture and Interact with you
@thyagtubes
@thyagtubes 4 жыл бұрын
Lecture starts at 9:04
@ilyasgaripov3686
@ilyasgaripov3686 5 жыл бұрын
Very helpful, thank you
@calengr1
@calengr1 6 жыл бұрын
main memory starts at 7 40
@ankitvashishtha7410
@ankitvashishtha7410 7 жыл бұрын
Hi Prof. Onur Mutlu, All the facts beautifully explained. Hats Off! Thanks for the lectures. Now, I have two doubts, first how memory controller is selecting the rank no. from given address? You have shown only row, channel. & column selection from a coming address) ( Time : 1:19:22 - kzbin.info/www/bejne/f4bOaqJvrNuLZ7s ) Second doubt: Do you have any video explaining the Memory Controller & PHY interconnection with working with DRAM Chip. How different timing signals like DQS etc work together? If yes please share the link.
@noahgoldstein3951
@noahgoldstein3951 2 жыл бұрын
If you pipeline subarray access in banks won't you essentially end up thrashing the global row-buffer? Seems like this will increase the frequency of precharging (and then power consumption AFAICT).
@PrinceKumar-bi6vq
@PrinceKumar-bi6vq 7 жыл бұрын
In THREAD CLUSTERING MEMORY SCHEDULING My doubts are - 1. Which threads are you refering here ? Is it hardware thread or kernel/user thread? 2. How does memory controller gets the information related to thread?
@CMUCompArch
@CMUCompArch 7 жыл бұрын
1. It is hardware threads. More specifically, hardware context ID. 2. The hardware context ID is communicated with each request to the memory controller. I would suggest reading earlier works on the topic of thread-aware memory scheduling, which cover such information in more detail: Mutlu and Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007. people.inf.ethz.ch/omutlu/pub/stfm_micro07.pdf Mutlu and Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems", ISCA 2008. people.inf.ethz.ch/omutlu/pub/parbs_isca08.pdf
@lebanbo55
@lebanbo55 9 жыл бұрын
I know.
@lebanbo55
@lebanbo55 9 жыл бұрын
Why there are so many "@"?
@hrqasim
@hrqasim 6 жыл бұрын
I don't get the point that each column gives 8 bits?? Column decoder is also a mux which selects one of the bits in row buffer??
@sujayyadalam9842
@sujayyadalam9842 6 жыл бұрын
A single row buffer consists of multiple bytes. For example, you can have a DRAM with 8kB row buffers. The column decoder is used to select the block (again block size can be different, for example 64 bytes) in the row.
@zaferesen1253
@zaferesen1253 6 жыл бұрын
I think in the images it is abstracted to show a single bit; but under the hood, the columns actually consist of 8 stacked memory cells (connected to the same row-column intersection).
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