Lecture 22: Memory Controllers - Carnegie Mellon - Comp. Arch. 2015 - Onur Mutlu

[@joechang8696]

In hind sight, the right time for Intel to integrate the memory controller would have probably been with the Pentium 4, give how high the P4 frequency was actually capable of. However, during early planning phase, the thought was that Willamatte frequency was going to be 1200-1400MHz. The plan was also to use Rambus memory, which was capable of high bandwidth. Because Intel just made the commitment to a new bus for P4 (quad-pumped version of the PPro bus and other enhancements) Intel did not want change the bus again, hence the delay to Nehalem. The Intel strategy for logistical simplicity was that a new processor could use the previous north bridge, and a new north bridge could support both the current and next processor. Of course, this cannot be adhered to for an extended period, it could be for a 3-4 year stretch.

[@JonMasters]

SPEC is still very important. While largely irrelevant, software industry dinosaurs still use it, meaning that those of us trying to promote adoption of ARMv8 servers have to go through contrived nonsense to make SPEC look good for the one time it will be run.

[@10ghznetburst]

Funny how moving the memory controller on chip was a no-brainer back when AMD did it, but now we again are moving them off chip with CXL and OMI...

[@PrinceKumar-bi6vq]

In THREAD CLUSTERING MEMORY SCHEDULING My doubts are - 1. Which threads are you refering here ? Is it hardware thread or kernel/user thread? 2. How does memory controller gets the information related to thread?

[@linelogic1699]

A thread here, means a Processing Engine ( PE ). It could be one core or one thread in a multi-thread CPU. A single stream of instructions.

[@EvilSapphireR]

@@linelogic1699 that's a who lotta words for a hardware thread, something the guy directly asked. I love deliberate academic obscuration.