Lecture 3 Introduction (Contd.)

[@nilashishchakraborty3983]

At 13:21 the final carry will be a output of OR not NOR

[@pallabmandal243]

Correct

[@harikishorerp6237]

@21:48 the last stage of D flipflop is not NOR gates. I think they are NAND gates. Correct me if I am wrong. Thank you.

[@AkshatPadhega...]

Can be made either with NAND or with NOR but sir combined both that is doubtful me too 😅

[@vimala8508]

In the D flip flop circuit it is NANDs gate not NOR gates 21.00

[@rajneshlodhirajput1025]

sir kindly correct it at the 21: 51 it is NAND gate not nor , i got confused

[@PrithaMajumder]

INTRODUCTION

[@shubhamide]

what do you mean by that comment?

[@surjadiptomukherjee5549]

are pritha di

[@nehamarne356]

@22:31 in start its not nand get it should be and

[@abinashgupta670]

bhai kya kya gate laga raha hai !!

[@manaskaskar1850]

Pura toh sahi hai

[@RamaKrishna-fp7yd]

Nuv etla iit professor ayinav ra 😒🤦🏻‍♂️

[@manikantareddy6588]

Same doubt bro naakuda😶

[@surendrasmiley3487]

😂😂enty bro antha maata anesavh

[@basicmallu]

worst teaching, he dont care whether the topics is properly explained or not