Lecture 9: Interrupts

[@iliassfe]

For the last two months I'm trying to understand the logic behind ARM MCUs, so I ran across many tutorials. By far you have the best presentations! Thank you my friend!

[@creedo8301]

10:48 why in the address 0x00000064 does it contain the address 0x0800030D and not 0x0800030C ? can anyone help please

[@embeddedsystemswitharmcort9051]

The least significant bit must be 1 to indicate that the processor is to run in Thumb mode. ARM Cortex-M only support Thumb instructions.

[@rileystewart9165]

Although the voice in the video is not perfect, it's surprisingly good for a robot, and considering the content and explaination was excellent, I'm very happy with the final product! Subscribed.

[@embeddedsystemswitharmcort9051]

Glad to know that. I have started to use my own voice now.

[@ulysses_grant]

Man, I owe you a beer. Really.

[@minghanqiu1095]

Buy his book then

[@ulysses_grant]

@@minghanqiu1095 I did!

[@eestop2978]

can we get the slides please? thank you for the video.

[@Cpu-w5f]

This is a pure gold .

[@omar-shukrimcintosh9097]

Thank you robot for the clear explanation, using an almost dead, emotionless voice.

[@КонстантинМатвеев-д8ц]

Voice like a melted butter

[@embeddedsystemswitharmcort9051]

Yeah, in the future, I will use my own voice.

[@paulg.3067]

What robot software reads that text? It has an amazing natural pronunciation

[@krish2nasa]

Excellent Explanation, Thank you very much Prof Yifeng

[@DanielBaluta]

at 1:23 the phone analogy doesn't really work. If you pick up the phone before a call arrives then the sender will get a busy tone.

[@embeddedsystemswitharmcort9051]

You pick up the phone and hang it up if there is no incoming call.

[@abnass8559]

Thank you Dr. Zhu

[@coolwinder]

9:10 - Interrupt Vector Table & Example

[@suseelkousic6787]

In the interrupt handler function why are we setting the Bit in PR register at last ?

[@parthshinde5966]

13:46 Isn't Stack Last-in-First-out? According to explanation here, it looks like registers are stacked inversely because top of the stack is popped first.

[@embeddedsystemswitharmcort9051]

Cortex-M4 uses full descending stack by default.

[@parthshinde5966]

@@embeddedsystemswitharmcort9051 yes that is true. You are correct. I had lack of conceptual knowledge

[@Ulbert86]

What a great presentation! Excelent work!

[@embeddedsystemswitharmcort9051]

Thank you. I am glad you like it.

[@richardqqq176]

you make the ARM architecture story sound so clear

[@longwang3271]

Thanks! Very well explained!

[@shiningmickey]

Thanks for the nice video. In the nested interrupt example, why isn't Pending Register for EXTI3 becomes 1 again when it is stacked and waited for DMA1_Channel2 interrupts to be finished?

[@MrKaviraj75]

Is a robot reading the text?

[@superiorphi5778]

yes, its to eliminate people potentially complaining about Prof Yifeng Zhu's accent

[@romandavydov8684]

Robots everywhere these days....

[@BillCipher1337]

@@superiorphi5778 his accent isnt even that bad ... :/

[@tomhyhlik1788]

better robot than strong accent

[@embeddedsystemswitharmcort9051]

KZbin does not allow voice over an existing video. Do you folks know a good solution?

[@footballCartoon91]

@16:18 so the process of preserving environment variable(by pushing the aforementioned registers onto the stack) cost the CPU 32-bits of addresses.. while unstacking, does it cost cpu 32-bits of address line too? And also does ISR only do two instructions? (BX and LR).. How much address the CPU need for this?.. So why does we need to offset 64bits of address when we want to determine the address of program ISR? (64+4xn) From what I understand, stacking environment variables cost 32bits of address, which corresponds to 4 bits of address is used to push a value from a register to the stack.. Does this means BX and LX cost the CPU 4 bits of address each? If that the case to find the next address of ISR program would be 32+4+32+4xn. if not then, 32(for stacking)+32(for unstacking)+4(for BX and LX or any other ISR operations that might require only 4bits of address)*n(nth element of an array of ISR)

[@caioheitor3181]

Very good class with several amazing details !!!

[@OverlordNibble]

perfect movie for a rainy day

[@paulg.3067]

yes, with a girlfried in the arms, on the sofa and a cup of potatochips, fine selection of cheese and a bottle Chateau Lafite 1936...

[@lmaooo4759]

@@paulg.3067

[@footballCartoon91]

@15:41 why he is saying that the program ISR (Interrupt Service Routine) or Interrupt Handler has the size of 32 bytes but demonstrate it in 32 bits? if 1 opcode is one byte(8bits), and 1 data line is 64 bits.. 1 bit of address line can have an instruction(opcode) + data =64 bits 4 bits of address line= 4*64 =256 bits or 1 byte.. 8 bits of address line= 2 bytes if 32 bits of address line= 8 bytes.. oh ok so i understand this ISR program requires 8 bytes of address line.. Or 32 address space

[@jashielp.estrada7163]

Wow. Now I understand interrupts for my job interview XD.

[@da_druuskee7709]

did you get the job?

[@jashielp.estrada7163]

@@da_druuskee7709 yes I got it. :)

[@kennyecheverry5684]

i'm reviewing for that right now! Any advice? XD

[@ashwin372]

are you on LinkedIn. i sent you a request please accept i am From India

[@VitaminVS]

These are great videos. Is the book having similar explanation?

[@coderhex1675]

in 17:21 there shuldn't be a pending state. I observed in my program. If you are pointing that this pending bit is flipping 1 to 0 so quickly when we enter ISR12 that we cannot observe this case, again there is no 1 to 0 switch. Could you provide me your proof?

[@embeddedsystemswitharmcort9051]

This is an interesting question. The "Interrupt Set-pending Registers" and "Interrupt Clear-pending Registers" works in pairs to set or clear the pending state of an interrupt. You can find more information in Cortex -M4 Devices Generic User Guide.

[@coderhex1675]

@@embeddedsystemswitharmcort9051 sorry for my bad english but did you completelly understand what i am tying to tell you? If i couldnt, i can tell with other sentence. I appriceate your videos so i respect you a lot. Could you provide me the exact sentence in the document?

[@hubert_c]

Very good analogy for polling vs interrupt.

[@VAXHeadroom]

There is a key piece of information here which the ARM documentation on the NVIC does NOT answer: Is a higher priority number more or less urgent? Thank you for including the answer in this video!

[@embeddedsystemswitharmcort9051]

Great to know that.

[@Molnihun96]

Lower value means higher priority. Configurable values range from 0 to 15, while non-configurable high-priority interrupts can even have negative values. -3 being the highest priority. You can check these informations in the RM0090 reference manual under "table 61." ("External interrupt/event controller (EXTI)" section).

[@Jarrod_C]

wait is there an error at 11:42 because the address of the pointer to the ISR is 30D but the address of the ISR is 30C? What is going on here?

[@chimeraSTEM]

The slide is correct. The address to jump to must have the least significant bit of the least significant bite set to 1 to indicate the processor is executing in THUMB mode. The video does explain this.

[@victorial5141]

this channel is underrated

[@ngocmanprocoder]

64 + 4 *n , could you clarify the formula in more details, please? Thanks a million.

[@kingfalconkhan]

Wahuuuu amazing video Prof. Zhu... Thanks a lot..!

[@embeddedsystemswitharmcort9051]

Most welcome!

[@גלרייפן]

Does NVIC clear the icpr register by itself? Or is it the responsability of the interrupt handler?

[@messiweltmeista]

Outstanding video, thank you very much

[@hakuhakuji]

15:38 When an interrupt is done, a BX LR instruction is executed? But how does LR register receives the value of PC before the interrupt? Does it happen automatically? Or we need to get it from the stack thst was previously saved?

[@embeddedsystemswitharmcort9051]

The hardware automatically preserves LR value onto the stack, and sets LR to a new value to indicate which stack is used. This happens automatically.

[@hakuhakuji]

@@embeddedsystemswitharmcort9051 Thank you for the fast answer. I think saying that exceptional return value EXC_RETURN is stored there during the interrupt handling is better. Loading this value by BX will automatically start unstacking and subsequently load the right value to PC. I've done some research on my own :)

[@axela.9247]

Great video

[@vishnuchittapu8459]

when dma interrupt is performing whether exti3 is in active state or pending state

[@zoya3396]

Thank you! very clear and helpfull!

[@mohangovind700]

Excellent Presentation about NVIC i have ever seen...............................

[@rindaman9151]

Can I Get The PPT?

[@Dads_Crown]

in intrupt calculation what is mean by 64

[@Wyvernnnn]

Ah; $67 without shipping for the book. You should publish an epub version Pr. Shu

[@debajyotichatterjee5863]

17:30 -- Is it possible to disable Interrupt nesting in the ARM Cortex-M Microcontrollers? Is it required to be performed in software? Or is there a way to configure the NVIC to be able to block the other IRQs once a IRQ is being serviced?

[@jerrysundin8425]

There is never a reason for this as long as you sort priorities according to needs.

[@LubosMedovarsky]

Priority vs. subpriority depth is a compromise at cost of subpriority bit depth, and is configurable in most Cortex-Ms.

[@emilyhuang2759]

So what is preemption

[@BeautifulSennery]

In explain sram mapping, it states stack going down, heap up. That,s only one stack. When in MSP and PSP, how sram is configured?

[@embeddedsystemswitharmcort9051]

MSP and PSP are configured by software during the booting process, specifically by startup.s.

[@nancywangeci8189]

A very good lesson .... you explain so well ... thanks and GOD bless.

[@Caffeine_Addict_2020]

incredible explanation

[@ShivamGupta-qe1me]

Thanks sir for making this video. keep uploading more.

[@manhtieu6569]

Can you explan that why stacking and unstacking take 12 cycle , again tail chain take 6 cycle? Please ...

[@embeddedsystemswitharmcort9051]

community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/beginner-guide-on-interrupt-latency-and-interrupt-latency-of-the-arm-cortex-m-processors

[@manhtieu6569]

thank you very much

[@mukundhanamshet935]

Awesome video thank you

[@mortenlund1418]

Great explanaition. Thank you for your effort and great teaching skills. Best wishes.

[@tomhyhlik1788]

thank you for such great explanation.

[@embeddedsystemswitharmcort9051]

You are welcome!

[@haideralam1]

Only complain with you is Robo voice, please upload same video in your original voice

[@孫文良-f5c]

very good tutorial!

[@nelsoncastillo4506]

very good tutorial video!!!

[@himmelblau1906]

awesome lecture! thanks!

[@embeddedsystemswitharmcort9051]

You are welcome!

[@battellone]

excellent

[@ningben7161]

Excellent Explanation, Thank you very much Prof Yifeng~~~

[@petros4225]

Sciencephille the AI? what are you doing here?

[@igoragoli]

Please consider narrating the videos instead of using an automatic voice. Other than that, great video!

[@embeddedsystemswitharmcort9051]

Noted!

[@kaviyathangaraj8242]

what is meant by 64 in interrupt calculation (64+4*n)?

[@venkatanagateja3072]

thank u

[@TheRojo387]

That Cortex M-4 system must be big-endian, no doubt!

[@Jonathan-ru9zl]

The automatic voice is unbearable please replace the audio

[@mahmutbostan6080]

hi bro What is the maximum interrupt speed for stm32f767zi?

[@KirstaRunner]

Watch the video at 1.5 or 2.0 speed.

[@khaledhumood7987]

i emailed youtube to add 3 and 3.5 speeds

[@saturdaysequalsyouth]

Can't listen to this synthesized voice...

[@dontaskiwasbored2008]

downvote for robot voice

[@khaledhumood7987]

what was he saying??