LEF file | Technology file | Description of various files used in VLSI Design | session -2

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Team VLSI

Team VLSI

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Пікірлер: 46
@radhikasingh4065
@radhikasingh4065 4 жыл бұрын
Very useful sir your shared information, Thanks for sharing your Knowledge with us
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Thanks @Radhika! Keep supporting...
@bhargavisudina4848
@bhargavisudina4848 Жыл бұрын
Hii Uthkarsh dse topics are soo useful for freshers.
@TeamVLSI
@TeamVLSI Жыл бұрын
Hi @bhargavi, Thanks for you recommendation!
@chunhuadeng8770
@chunhuadeng8770 4 жыл бұрын
Very good video, very helpful. Thanks
@TeamVLSI
@TeamVLSI 4 жыл бұрын
You're welcome!
@saint2091
@saint2091 4 жыл бұрын
Can you also upload a video tutorial on how to generate LEF file in Virtuoso?
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Ok, I will try.
@saint2091
@saint2091 4 жыл бұрын
Can you please explain what is implant layer in LEF file? and where its used?
@dilliganeshbabu3301
@dilliganeshbabu3301 4 жыл бұрын
Very useful videos. Can you make a tutorial videos on Static Timing Analysis? It will be very useful.
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Thanks @DILLIGANESH Sure I have a plan to explain STA very soon.
@csS0nNer
@csS0nNer Жыл бұрын
Thanx for the video. Which tool do you use to edit LEF files?
@jetli4696
@jetli4696 3 жыл бұрын
thank you from China
@TeamVLSI
@TeamVLSI 3 жыл бұрын
You are most welcome Jet li. Keep learning keep supporting.
@mr_official_tech7734
@mr_official_tech7734 2 жыл бұрын
Where can we see the which technology we are using like 5nm chip or 7nm chi etc...??
@akhilmalik666
@akhilmalik666 5 жыл бұрын
Hi.. resistance value of metals layer will be different for each RC corner . And resistance in tech lef has only 1 resistance value
@TeamVLSI
@TeamVLSI 5 жыл бұрын
Alright Akhil, The mentioned value of resistance in technology LEF or in .tf is the typical resistance value for each metal layers. But yes there is variations in resistance in different RC corners.
@anushaeerlapati004
@anushaeerlapati004 2 жыл бұрын
hi in .lib file also we have cell names,units and pin details and in .lef file also we have the same so, what is the diff?
@aparnareddy7450
@aparnareddy7450 2 жыл бұрын
Sir.....can you please make a tutorial on DRT analysis in Cadence...?
@gurramsanjeev1301
@gurramsanjeev1301 4 жыл бұрын
nice sir ,small request sir do video on double patterning
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Thanks Gurram. keep supporting. We will do that.
@snkhy5631
@snkhy5631 3 жыл бұрын
thank you sir
@TeamVLSI
@TeamVLSI 3 жыл бұрын
Most welcome
@anujparekh752
@anujparekh752 10 ай бұрын
What is difference between .lef and .tf? how they exactly have some difference?
@anujparekh752
@anujparekh752 5 ай бұрын
Hey please answer
@shivamshrivastava1794
@shivamshrivastava1794 2 жыл бұрын
Hello Sir, what is the unit of Resistance(RPERSQ) is it nenometer or something else?
@TeamVLSI
@TeamVLSI 2 жыл бұрын
Hi Shivam, Resistance is always measured in Ohm.
@akhilmadankar7578
@akhilmadankar7578 4 жыл бұрын
what is the masterslice and where is it used ? ( point 6th in technology lef)
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Hi Akhil, Masterslice layer is typically poly layers and only needed if the Macro has pins on Poly layer. If masterslice layer is defined , one cut layer must be defined between masterslice layer and first routing layer.
@StayInBliss
@StayInBliss 5 жыл бұрын
what a detailing
@TeamVLSI
@TeamVLSI 5 жыл бұрын
Question is not clear. please ask along with some reference.
@StayInBliss
@StayInBliss 5 жыл бұрын
@@TeamVLSI it's not a question I am saying very good detailing
@TeamVLSI
@TeamVLSI 5 жыл бұрын
Ohhh Thanks a lot.
@gauravsharma-dy7gs
@gauravsharma-dy7gs 4 жыл бұрын
Can u upload one video on SPEF file? I have a doubt in that.
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Hi Gaurav, Thanks for reminding. I will explain SPEF file soon.
@abhinavagarwal4924
@abhinavagarwal4924 Жыл бұрын
which file contains information related to frequency?
@TeamVLSI
@TeamVLSI Жыл бұрын
Hi Abhinav, All the clock constraints for PnR come in form of SDC file from synthesis team.
@abhinavagarwal4924
@abhinavagarwal4924 Жыл бұрын
Thank you
@abhavsvelidi8828
@abhavsvelidi8828 2 жыл бұрын
What is via in .tf file?
@ravivaradarajan1425
@ravivaradarajan1425 4 жыл бұрын
Can you convert a technology LEF file into a .tf file?
@abdallahtorky9352
@abdallahtorky9352 2 жыл бұрын
can you help me with that?
@arunpandiyananbarasu1455
@arunpandiyananbarasu1455 4 жыл бұрын
What is meant by foreign in Lef
@TeamVLSI
@TeamVLSI 4 жыл бұрын
Hi Arun, As per the LEF reference manual FOREIGN foreignCellName [pt [orient]] Specifies the foreign (GDSII) structure name to use when placing an instance of the macro. The optional pt coordinate specifies the macro origin (lower left corner when the macro is in north orientation) offset from the foreign origin. The FOREIGN statement has a default offset value of 0 0, if pt is not specified. The optional orient value specifies the orientation of the foreign cell when the macro is in north orientation. The default orient value is N (North).
@graphic_artist06
@graphic_artist06 Жыл бұрын
Can you please share me the .lef file that would be helpful for my project
@kranthikumar339
@kranthikumar339 2 жыл бұрын
How to download this pdf in teligram
@TeamVLSI
@TeamVLSI Жыл бұрын
Hi Kranthi, Sorry those slides are not downloadable. better to make your own note if needed from video.
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